Power-optimal pipelining in deep submicron technology

Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04

Volumn , Issue , 2004, Pages 218-223

  Heo, Seongmoo ^a   Asanović, Krste ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Pipelining; Power Scaling; Supply Voltage Reduction

Indexed keywords

ENERGY MANAGEMENT; ENERGY UTILIZATION; LEAKAGE CURRENTS; LOGIC GATES; PARALLEL PROCESSING SYSTEMS; THRESHOLD VOLTAGE;

PIPELINING; POWER SAVINGS; POWER SCALING; SUPPLY VOLTAGE REDUCTION;

MICROPROCESSOR CHIPS;

EID: 16244395794     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1013235.1013291     Document Type: Conference Paper

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