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Volumn 2005, Issue , 2005, Pages 28-33

Defective behaviours of resistive opens in interconnect lines

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CROSSTALK; DEFECTS; ELECTRIC RESISTANCE; LARGE SCALE SYSTEMS;

EID: 28444479615     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ETS.2005.13     Document Type: Conference Paper
Times cited : (39)

References (19)
  • 2
    • 0022527822 scopus 로고
    • Topology dependence of floating gate faults in MOS integrated circuits
    • January 30
    • Renovell, M., and Cambon, G., "Topology Dependence of Floating Gate Faults in MOS Integrated Circuits," Electronics Letters, Vol. 22, No, 3, pp. 152-153, January 30, 1986.
    • (1986) Electronics Letters , vol.22 , Issue.3 , pp. 152-153
    • Renovell, M.1    Cambon, G.2
  • 4
    • 0030217085 scopus 로고    scopus 로고
    • DDQ testing of single floating gate defects using a two-pattern vector
    • DDQ testing of single floating gate defects using a two-pattern vector" Electronics Letters, Volume: 32, Issue: 17, pp, 1572 -1574, 1996.
    • (1996) Electronics Letters , vol.32 , Issue.17 , pp. 1572-1574
    • Champac, V.H.1    H., V.2    Figueras, J.3
  • 6
    • 0028392267 scopus 로고
    • Electrical model of the floating gate defect in CMOS ICs: Implications on IDDQ Testing
    • March
    • V.H. Champac, A. Rubio and J. Figueras, "Electrical model of the floating gate defect in CMOS ICs: Implications on IDDQ Testing", IEEE Trans. Computed Aided Design, Vol 13, pp. 359-369, March, 1994.
    • (1994) IEEE Trans. Computed Aided Design , vol.13 , pp. 359-369
    • Champac, V.H.1    Rubio, A.2    Figueras, J.3
  • 7
    • 0033319644 scopus 로고    scopus 로고
    • Voltage and current-based fault simulation for interconnect open defects
    • December
    • H. Konuk, "Voltage and current-based fault simulation for interconnect open defects", IEEE Trans, On Computed-Aided Design of integrated circuits and systems, Vol. 18, N.12, pp. 1768-1779, December, 1999.
    • (1999) IEEE Trans, on Computed-aided Design of Integrated Circuits and Systems , vol.18 , Issue.12 , pp. 1768-1779
    • Konuk, H.1
  • 9
    • 0029694994 scopus 로고    scopus 로고
    • An unexpected factor in testing for CMOS opens: The die surface
    • Konuk, H.; Ferguson, F.J.;, "An unexpected factor in testing for CMOS opens: the die surface", VLSI Test Symposium, pp. 422 - 429, 1996.
    • (1996) VLSI Test Symposium , pp. 422-429
    • Konuk, H.1    Ferguson, F.J.2
  • 10
    • 0001170686 scopus 로고
    • Residual charge on the faulty floating gate CMOS transistor
    • Johnson, S.;, "Residual charge on the faulty floating gate CMOS transistor", International Test Conference, pp. 555-561, 1994.
    • (1994) International Test Conference , pp. 555-561
    • Johnson, S.1
  • 11
    • 0036446204 scopus 로고    scopus 로고
    • On testing of interconnect open defects in combinational logic circuits with stems of large fanout
    • Reddy, S.M.; Pomeranz, I.; Huaxing Tang; Kajihara, S.; Kinoshita, K.;, "On testing of interconnect open defects in combinational logic circuits with stems of large fanout", International Test Conference, pp, 83-89,2002.
    • (2002) International Test Conference , pp. 83-89
    • Reddy, S.M.1    Pomeranz, I.2    Tang, H.3    Kajihara, S.4    Kinoshita, K.5
  • 12
    • 0033750909 scopus 로고    scopus 로고
    • Detectability conditions for interconnection open defects
    • V.H. Champac, A. Zenteno, "Detectability conditions for interconnection open defects", VLSI Test Symposium, pp. 305-311, 2000.
    • (2000) VLSI Test Symposium , pp. 305-311
    • Champac, V.H.1    Zenteno, A.2
  • 14
    • 0024663491 scopus 로고
    • Quiescent power supply current measurement of CMOS IC detection
    • May
    • C.F. Hawkins et al, "Quiescent power supply current measurement of CMOS IC detection", IEEE Trans. On industrial electronics,Vol.36,N.2,pp. 211-218,May,1989.
    • (1989) IEEE Trans. on Industrial Electronics , vol.36 , Issue.2 , pp. 211-218
    • Hawkins, C.F.1
  • 16
    • 84948428485 scopus 로고    scopus 로고
    • Fault models for speed failures caused by bridges and opens
    • Chakravarty, S.; Jain, A.; "Fault models for speed failures caused by bridges and opens", VLSI Test Symposium, pp. 373-378, 2002.
    • (2002) VLSI Test Symposium , pp. 373-378
    • Chakravarty, S.1    Jain, A.2
  • 17
    • 3142664872 scopus 로고    scopus 로고
    • New test methodology for resistive open defect detection in memory address decoders
    • Azimane, M.; Majhi, A.K.;"New test methodology for resistive open defect detection in memory address decoders", VLSI Test Symposium, pp. 123-128, 2004.
    • (2004) VLSI Test Symposium , pp. 123-128
    • Azimane, M.1    Majhi, A.K.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.