Process-variability aware delay fault testing of ΔVT and weak-open defects

Proceedings of the European Test Workshop

Volumn 2003-January, Issue , 2003, Pages 85-90

  Arumi Delgado D ^a   Rodriguez Montanes R ^a   De Gyvez, J P ^b   Gronthoud, G ^b  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

Circuit faults; Circuit simulation; Circuit testing; CMOS technology; Electronic equipment testing; Fault detection; Integrated circuit testing; Laboratories; Propagation delay; Semiconductor device modeling

Indexed keywords

CIRCUIT SIMULATION; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; ELECTRONIC EQUIPMENT; ELECTRONIC EQUIPMENT TESTING; EQUIPMENT TESTING; FAULT DETECTION; LABORATORIES; OSCILLATORS (ELECTRONIC); SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE TESTING; SEMICONDUCTOR DEVICES;

CIRCUIT FAULTS; CIRCUIT TESTING; CMOS TECHNOLOGY; DELAY-FAULT TESTING; FAULT-FREE CIRCUITS; PROCESS VARIABILITY; PROPAGATION DELAYS; STATISTICAL DELAYS;

INTEGRATED CIRCUIT TESTING;

EID: 33744478301     PISSN: 15301877     EISSN: 15581780     Source Type: Conference Proceeding    
DOI: 10.1109/ETW.2003.1231673     Document Type: Conference Paper

References (14)

1. M. Eisele, et al. "The Impact of Intra-Die Device Parameter Variations on Path Delays and on the Design for Yield of Low Voltage Digital Circuits", IEEE Trans. on Very Large Scale Integ. (VLSI) Systems, Vol. 5. No. 4, December 1997.
2. K. Heragu, J. H. Patel and V. D. Agraval, "A Test Generator for Segment Delay Faults", Twelfth Int. Conf. on VLSI Design, pp. 484-491, 1999.
3. S. Kajihara, et al. "A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths", Int. conf. on VLSI Design, pp. 82-87, January 1997.
4. W.-N. Li, S. M. Reddy, S. K. Sahni, "On Path Selection in combinational Logic Circuits", Design Automation Confer., Proceedings, 25th ACM/IEEE, pp. 142-147, 1988.
5. A. K. Majhi, et al., "Line Coverage of Path Delay Faults", Trans. on Very Large Scale Integ. (VLSI) Syst., IEEE, Vol 8, pp 610-614, Oct 2000..
6. V. H.-W. Meyer, W. Anheier and A. Sticht, "Non-Robust Delay Test Pattern Generation Based on Stuct-at TPG", IEEE Int. Conf. on Electronics, Circuit and Systems, ICECS, Volume 2, pp. 1007-1010, 2001.
7. M. Michael and S. Tragoudas, "Functional-Based ATPG for Path Delay Faults", Southwest Symposium on Mixed-Signal Design, SSMSD, pp. 159-164, 2000.
8. W. Moore, G. Gronthoud, K. Baker, M. Lousberg, "Delay-Fault Testing and Defects in Deep Sub-Micron ICs - Does Critical Resistance Really Mean Anything?", Int. Test. Conf., pp. 95-104, 2000.
9. I. Pomeranz and S. M. Reddy, "A Flexible Path Selection Procedure for Path Delay Fault Testing", VLSI Test Symp., pp. 152-159, 1999.
10. A. K. Pramanick and S. M. Reddy, "On the Fault Coverage of Gate Delay Fault Detecting Tests", IEEE Trans. on Comp. Aided Des. of Integ. Circ. and Syst., Vol. 16 No. 1, Jan. 1997.
11. M. Sharma and J. H. Patel, "Testing of Critical Paths for Delay Faults", Int. Test. Conf., pp. 634-641, 2001.
12. H. Wittmann and M. Henftling, "Path Delay ATPG for Standard Scan Design", European Proceedings EURO-DAC, with EURO-VHDL, pp. 202-207, 1995.
13. J. Pineda de Gyvez and R. Rodríguez-Montañés, "Threshold Voltage Mismatch ?VT Fault Modeling," VLSI Test Symposium, pp.145-150, 2003.
14. R. Rodríguez-Montañés, P. Volf, J. Pineda de Gyvez, "Resistance Characterization for Weak Open Defects" IEEE Design&Test of Computers, pp. 18-26, Sept.-Oct., 2002