A small, fast and low-power register file by bit-partitioning

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2005, Pages 40-49

  Kondo, Masaaki ^a   Nakamura, Hiroshi ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BIT-PARTITIONING; INSTRUCTION LEVEL PARALLELISM (ILP); REGISTER ENTRY; REGISTER FILE;

DELAY CIRCUITS; ENERGY UTILIZATION; PROBLEM SOLVING; PROGRAM PROCESSORS;

ELECTRIC POWER DISTRIBUTION;

EID: 28444458474     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2005.3     Document Type: Conference Paper

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