Design space of register renaming techniques

IEEE Micro

Volumn 20, Issue 5, 2000, Pages 70-83

  Sima, DezsÖ ^a  

^a OBUDA UNIVERSITY   (Hungary)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; DATA ACQUISITION; DATA RECORDING; DATA STRUCTURES;

REGISTER RENAMING; WRITE AFTER READ (WAR); WRITE AFTER WRITE (WAW);

PROGRAM PROCESSORS;

EID: 0034273716     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/40.877952     Document Type: Article

References (45)

1. B.R. Rau and J.A. Fisher, "Instruction Level Parallel Processing: History, Overview and Perspective," J. Supercomputing, Vol. 7. No. 1, 1993, pp. 9-50.
2. P.E. Smith and G.S. Sohi, "The Microarchitecture of Superscalar Processors," Proc. IEEE, IEEE Press, Piscataway, N.J., Vol. 83, No. 12, Dec. 1995, pp. 1609-1624.
3. D. Sima, T. Fountain, and P. Kacsuk, Advanced Computer Architectures, Addison Wesley Longman, Harlow, England, 1997.
4. R.M. Tomasulo, "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," IBM J. Research and Development, Vol. 11, No. 1, 1967, pp. 25-33.
5. G.S. Tjaden and M.J. Flynn, "Detection and Parallel Execution of Independent Instructions," IEEE Trans. Computers, Vol. C-19, No. 10, 1970, pp. 889-895.
6. R.M. Keller, "Look-Ahead Processors," Computing Surveys, Vol. 7, No. 4, 1975, pp. 177-195.
7. D. Leibholz and R. Razdan, "The Alpha 21264: A 500 MIPS Out-of-Order Execution Microprocessor," Proc. Compcon, IEEE Computer Society Press, Los Alamitos, Calif., 1997, pp. 28-36.
8. G. Kurpanek et al., "PA-7200: A PA-RISC Processor with Integrated High Performance MP Bus Interface," Proc. Compcon, IEEE CS Press, 1994, pp. 375-382.
9. D. Hunt, "Advanced Performance Features of the 64-Bit PA-8000," Proc. Compcon, IEEE CS Press, 1995, pp. 123-128.
10. A.P. Scott et al., "Four-Way Superscalar PA-RISC Processors," Hewlett-Packard J., Aug. 1997, pp. 1-9.
11. G. Lesartre and D. Hunt, PA-8500: The Continuing Evolution of the PA-8000 Family, Hewlett-Packard Co., Palo Alto, Calif., 1998, pp. 1-11.
12. G.F. Grohoski, "Machine Organization of the IBM RISC System/6000 Processor," IBM J. Research and Development, Vol. 34, No. 1, 1990, pp. 37-58.
13. S. White and J. Reysa, PowerPC and POWER2: Technical Aspects of the New IBM RISC System/6000, IBM Corp., Austin, Texas, 1994.
14. M. Becker et al., "The PowerPC 601 Microprocessor," IEEE Micro, Oct. 1993, pp. 54-68.
15. B. Burgess et al., "The PowerPC 603 Microprocessor," Comm. ACM, ACM Press, New York, Vol. 37, No. 6, 1994, pp. 34-42.
16. S.P. Song et al., "The PowerPC 604 RISC Microprocessor," IEEE Micro, Oct. 1994, pp. 8-17.
17. D. Ogden et al., "A New PowerPC Microprocessor for Low Power Computing Systems," Proc. Compcon, IEEE CS Press, 1995, pp. 281-284.
18. L. Gwennap, "IBM Crams Power2 Onto Single Chip," Microprocessor Report, Micro Design Resources, Sunnyvale, Calif., Vol. 10, No. 11, 1996, pp. 14-16.
19. D. Levitan et al., "The PowerPC 620 Microprocessor: A High Performance Superscalar RISC Microprocessor," Proc. Compcon, IEEE CS Press, 1995, pp. 285-291.
20. S.P. Song, "IBM's Power3 to Replace P2SC," Microprocessor Report, Micro Design Resources, Vol. 11, No. 15, 1997, pp. 23-27.
21. L. Gwennap, "MIPS R10000 Uses Decoupled Architecture," Microprocessor Report, Micro Design Resources, Vol. 8, No. 14, 1994, pp. 18-22.
22. L. Gwennap, "MIPS R12000 to Hit 300 MHz," Microprocessor Report, Micro Design Resources, Vol. 11, No. 13, 1997, pp. 1, 6-7, 17.
23. N. Patkar et al., "Microarchitecture of HaL's CPU," Proc. Compcon, IEEE CS Press, 1995, pp. 259-266.
24. L. Gwennap, "Intel's P6 Uses Decoupled Superscalar Design," Microprocessor Report, Micro Design Resources, Vol. 9, No. 2, 1995, pp. 9-15.
25. L. Gwennap, " Klamath Extends P6 Family," Microprocessor Report, Micro Design Resources, Vol. 11, No. 2, 1997, pp. 1, 6-8.
26. Pentium III Processor, Product Overview, Intel Corp, Santa Clara, Calif., 1999.
27. J.S. Liptay, "Design of the IBM Enterprise Sytem/9000 High-End Processor," IBM J. Research and Development, Vol. 36, No. 4, July 1992, pp. 713-731.
28. B. Burkhardt, "Delivering Next-Generation Performance on Today's Installed Computer Base," Proc. Compcon, IEEE CS Press, 1994, pp. 11-16.
29. Cyrix 686MX, Cyrix Corporation, Richardson, Texas, Order No. 94329-00, July 1997.
30. L. Gwennap, "NexGen Enters Market with 66-MHz Nx586," Microprocessor Report, Micro Design Resources, Vol. 8, No. 4, 1994, pp. 12-17.
31. M. Slater, "AMD's K5 Designed to Outrun Pentium," Microprocessor Report, Micro Design Resources, Vol. 8, No. 14, 1994, pp. 1-11.
32. B. Shriver and B. Smith, The Anatomy of a High-Performance Microprocessor, IEEE CS Press, 1998.
33. K. Diefendorff, "K7 Challenges Intel," Microprocessor Report, Micro Design Resources, Vol. 12, No. 14, 1998, pp. 1, 6-11.
34. L. Gwennap, "Nx686 Goes Toe-to-Toe with Pentium Pro," Microprocessor Report, Micro Design Resources, Vol. 9, No. 14, 1995, pp. 1, 6-10.
35. D. Sima, "Superscalar Instruction Issue," IEEE Micro, Sept.-Oct. 1997, pp. 29-39.
36. V. Popescu et al., "The Metaflow Architecture, " IEEE Micro, June 1991, pp. 10-13, 63-71.
37. T. Monreal et al., "Delaying Physical Register Allocation Through Virtual-Physical Registers," Proc. MICRO-32, IEEE CS Press, 1999, pp. 186-192.
38. S. Wallace and N. Bagheryadeh, "A Scalable Register File Architecture for Dynamically Scheduled Processors," Proc. 1996 Conf. Parallel Architectures and Compilation Techniques, 1996, pp. 179-184.
39. A. González et al., "Virtual Registers," Proc. Third Int'l Symp. High-Performance Computer Architecture, IEEE CS Press, 1997, pp. 364-369.
40. A. González, J. Gonzalez, and M. Valero, "Virtual-Physical Register," Proc. Fourth Int'l Symp. High-Performance Computer Architecture, IEEE CS Press, 1998, pp. 175-184.
41. S. Jourdan et al., "A Novel Renaming Scheme to Exploit Value Temporal Locality Through Physical Register Reuse and Unification," Proc. MICRO-31, IEEE CS Press, 1998, pp. 216-225.
42. J.E. Smith and A.R. Pleszkun, "Implementing Precise Interrupts in Pipelined Processors," IEEE Trans. Computers, IEEE CS Press, Vol. C-37, No. 5, 1988, pp. 562-573.
43. M. Johnson, Superscalar Microprocessor Design, Prentice Hall, Englewood Cliffs, N.J., 1991.
44. G.S. Sohi and S. Vajapayem, "Instruction Issue Logic for High Performance, Interruptible Pipelined Processors," Proc. 14th ISCA, IEEE CS Press, 1987, pp. 27-36.
45. D. Sima, "The Design Space of Shelving," J. Systems Architecture, Vol. 45, No. 11, 1999, pp. 863-885.