Register write specialization register read specialization: A path to complexity-effective wide-issue superscalar processors

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn 2002-January, Issue , 2002, Pages 383-394

  Toullec, Eric ^a   Rochecouste, Olivier ^a  

^a CAMPUS DE BEAULIEU   (France)

Author keywords

Clocks; Delay effects; Energy consumption; Frequency; Logic; Meteorological radar; Process design; Registers; Silicon; Transistors

Indexed keywords

CLOCKS; COMPLEX NETWORKS; DESIGN; DIGITAL ARITHMETIC; ELECTRIC POWER UTILIZATION; ENERGY UTILIZATION; FLUIDIZED BED COMBUSTION; HAND HELD COMPUTERS; INTEGRATED CIRCUIT DESIGN; METEOROLOGICAL RADAR; NETWORK ARCHITECTURE; PROCESS DESIGN; PROGRAM PROCESSORS; SILICON; TRANSISTORS; WAKES;

DELAY EFFECTS; FREQUENCY; GENERAL PURPOSE REGISTERS; LOGIC; PHYSICAL REGISTERS; PROCESSOR DESIGNERS; REGISTERS; SUPERSCALAR PROCESSOR;

COMPUTER ARCHITECTURE;

EID: 84948974859     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2002.1176265     Document Type: Conference Paper

References (21)

1. Rajeev Balasubramonian, Sandhya Dwarkadas, and David H. Albonesi. Reducing the complexity of the register ýle in dynamic superscalar processors. InProceedings of the 34th Annual International Symposium on Microarchitecture, December 2001.
2. M. Brown, J. Stark, and Y. Patt. Select-free instruction scheduling logic. In Proceedings of the 34th Annual International Symposium on Microarchitecture, December 2001.
3. Robert P. Colwell, Robert P. Nix, John J. OíDonnell, David B. Papworth, and Paul K. Rodman. A VLIW architecture for a trace scheduling compiler. In Proceedings of Second International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS II), October 1987.
4. Jose-Lorenzo Cruz, Antonio Gonzalez, Mateo Valero, and Nigel Topham. Multiple-banked register ýle architectures. In Proceedings of the 27th International Symposium on Computer Architecture, june 2000.
5. D. Ernst and T. Austin. Efýcient dynamic scheduling through tag elimination. In Proceedings of the 29th Annual International Symposium on Computer Architecture, May 2002.
6. Paolo Faraboschi, Geoffrey Brown, Joseph A. Fisher, Giuseppe Desoli, and Fred (Mark Owen) Homewood. Lx: A technology platform for customizable VLIW embedded processing. In Proceedings of the 27th Annual International Symposium on Computer Architecture, June 2000.
7. K. I. Farkas, P. Chow, N. P. Jouppi, and Z. Vranesic. The multicluster architecture: Reducing cycle time through partitioning. In Proceedings of the 30th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-97), December 1997.
8. D. Folegnani and A. Gonzalez. Energy-effective issue logic. In Proceedings of the 28th Annual International Symposium on Computer Architecture, June 30ñJuly 4, 2001.
9. R. Gonzalez and M. Horowitz. Energy dissipation in general purpose microprocessor. In IEEE Journal of Solid-State Circuits, september 1996.
10. G. Hinton, D. Sager, M. Upton, D. Boggs, D. Carmean, A. Kyker, and P. Roussel. The microarchitecture of the pentium4 processor. In Intel Technology Journal, 2001.
11. Richard E. Kessler. The Alpha 21264 microprocessor. IEEE Micro, 19(2):24-36, 1999.
12. S. Manne, A. Klauser, and D. Grunwald. Pipeline gating: Speculation control for energy reduction. In Proceedings of the 25th Annual International Symposium on Computer Architecture (ISCA-98), June 27ñJuly 1 1998.
13. Teresa Monreal, Antonio Gonzalez, Mateo Valero, Jose Gonzalez, and Victor Vinals. Dynamic register renaming through virtual-physical registers. Journal of Instruction-Level Parallelism, May 2000.
14. Subbarao Palacharla, Norman P. Jouppi, and J. E. Smith. Complexity-effective superscalar processors. In 24th Annual International Symposium on Computer Architecture, pages 206-218, 1997.
15. Andre Seznec. A path to complexity-effective wide-issue superscalar processors. In Technical Report IRISA PI 1411, August 2001.
16. Andre Seznec, Stephen Felix, Venkata Krishnan, and Yanos Sazeidès. Design tradeoffs for the ev8 branch predictor. In Proceedings of the 29th Annual International Symposium on Computer Architecture, May 2002.
17. Andre Seznec and Pierre Michaud. De-aliased hybrid branch predictors. Technical Report RR-3618, Inria, 1999.
18. J. Stark, M. D. Brown, and Y. N. Patt. On pipelining dynamic instruction scheduling logic. In Proceedings of the 33rd Annual International Symposium on Microarchitecture, December 2000.
19. Marc Tremblay, Bill Joy, and Ken Shin. A three dimensional register ýle for superscalar processors. In Proceedings of the 28th Annual Hawaii International Conference on System Sciences, Jan 1995.
20. Steven J. E. Wilton and Norman P. Jouppi. Cacti: An enhanced cache access and cycle time model. IEEE Journal of Solid-State Circuits, May 1996.
21. Victor Zyuban and Peter Kogge. The energy complexity of register ýles. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED-98), August 10-12 1998.