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Volumn 2003-January, Issue , 2003, Pages 384-389

The microarchitecture of a low power register file

Author keywords

Computer architecture; Energy consumption; Microarchitecture; Microprocessors; Out of order; Performance loss; Permission; Prefetching; Process design; Registers

Indexed keywords

ENERGY UTILIZATION; LOW POWER ELECTRONICS; MICROPROCESSOR CHIPS; POWER ELECTRONICS; PROCESS DESIGN;

EID: 1542359123     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPE.2003.1231931     Document Type: Conference Paper
Times cited : (20)

References (12)
  • 5
    • 21644475767 scopus 로고    scopus 로고
    • EV8: The post-ultimate Alpha
    • Sep.
    • J. Emer. EV8: The post-ultimate Alpha. Keynote at PACT, Sep. 2001.
    • (2001) Keynote at PACT
    • Emer, J.1
  • 10
    • 0346237756 scopus 로고    scopus 로고
    • An Integrated Cache Timing, Power, and Area Model
    • Feb.
    • P. Shivakumar et al. An Integrated Cache Timing, Power, and Area Model. WRL Research Report, Feb. 2002.
    • (2002) WRL Research Report
    • Shivakumar, P.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.