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Volumn , Issue , 2005, Pages 374-379

Influence of leakage reduction techniques on delay/leakage uncertainty

Author keywords

[No Author keywords available]

Indexed keywords

LEAKAGE REDUCTION TECHNIQUES; LEAKAGE UNCERTAINTY; MONTE-CARLO ANALYSIS;

EID: 27944460390     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (20)

References (13)
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  • 2
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    • B. Chatterjee, et al, "Effectiveness and Scaling Trends of Leakage Control Techniques for Sub-130nm CMOS Technologies", International Symp. On Low Power Electronics and Designs, pp. 122-127, Aug 2003
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  • 3
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    • S. Nerendra, et al, "Full-Chip Subthreshold Leakage Power Prediction and Reduction Techniques for Sub-0.18-um CMOS", IEEE Journal of Solid-State circuits, VOL. 39, No. 2, pp. 501-510, Feb. 2004
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    • Nerendra, S.1
  • 4
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    • Parameter variations and impact on circuits and microarchitecture
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    • Bokar, et al., " Parameter Variations and Impact on Circuits and Microarchitecture", Design Automation Conference, pp.338-342, June 2003
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    • A. Keshavarzi, et al, "Intrinsic Leakage In Deep Submicron CMOS ICs - Measurement-Based Test Solutions", IEEE Trans. On VLSI Systems, VOL. 8, No. 6, pp. 717-723, Dec. 2000
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    • Oct.
    • T. Chen, et al, "Comparison of Adaptive Body Bias (ABB) and Adaptive Supply Voltage (ASV) for Improving Delay and leakage Under the Presence of Process Variation", IEEE Transaction of VLSI Systems, Vol. 11, No. 5, pp.888-899, Oct. 2003
    • (2003) IEEE Transaction of VLSI Systems , vol.11 , Issue.5 , pp. 888-899
    • Chen, T.1
  • 7
    • 14844302557 scopus 로고    scopus 로고
    • Yield optimization with energy-delay constraints in low-power digital circuits
    • Dec
    • Y. Cao, et al, "Yield Optimization with Energy-Delay Constraints in Low-Power Digital Circuits", IEEE Conference on Electron Devices and Solid State Circuits, pp. 285-288, Dec 2003
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  • 9
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    • N. Sirisantana, et al, "High-Performance CMOS Circuits using Multiple Channel Length and Multiple Oxide Thickness", International Conference on Computer Design, pp. 227-232, Sep. 2000
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.