Yield optimization with energy-delay constraints in low-power digital circuits

2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003

Volumn , Issue , 2003, Pages 285-288

  Cao, Yu ^a   Qin, Huifang ^a   Wang, Ruth ^a   Friedberg, Paul ^a   Vladimirescu, Andrei ^a   Rabaey, Jan ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY CIRCUITS; DESIGN; ELECTRIC NETWORK ANALYSIS; ELECTRON DEVICES; INTEGRATED CIRCUIT MANUFACTURE; PARAMETRIC DEVICES; SOLID STATE DEVICES; THRESHOLD VOLTAGE;

ADVANCED TECHNOLOGY; ENERGY-DELAY TRADEOFFS; LOW-POWER DIGITAL CIRCUITS; MONTE CARLO ANALYSIS; PARAMETRIC VARIATION; PERFORMANCE VARIABILITY; STATISTICAL MODELING; YIELD OPTIMIZATION;

LOW POWER ELECTRONICS;

EID: 14844302557     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EDSSC.2003.1283533     Document Type: Conference Paper

References (7)

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