Implications of technology scaling on leakage reduction techniques

Proceedings - Design Automation Conference

Volumn , Issue , 2003, Pages 187-190

  Tsai, Y F ^a   Duarte, D ^b   Vijaykrishnan, N ^a   Irwin, M J ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Leakage reduction; Low power; Technology scaling

Indexed keywords

GATES (TRANSISTOR); LEAKAGE CURRENTS; VLSI CIRCUITS;

LEAKAGE REDUCTION TECHNIQUES;

POWER SUPPLY CIRCUITS;

EID: 0043136768     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/775832.775880     Document Type: Conference Paper

References (6)

1. Narendra, S., et al, "Scaling of stack effect and its application for leakage reduction," ISLPED, pp. 195-200, '01.
2. Keshavarzi, et al, "Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs," ISLPED, pp 207-212, 2001
3. Duarte, D, et al, "Evaluating Run-Time Techniques for Leakage Reduction", ASPDAC, pp. 31-38, 2002
4. Ye, Y., Borkar, S., and De, V., "A New Technique for Standby Leakage Reduction in High-Performance Circuits," Sym. on VLSI Circuits, pp. 40-41, 1998
5. Halter J., and Najm, F., "A Gate-level Leakage Power Reduction Method for Ultra Low Power CMOS Circuits, IEEE CICC, pp. 475-478, 1997.
6. Duarte, D, "Clock Network and Phase-Locked Loop Power Estimation and Experimentation", PhD Thesis, Penn State University, May. 2002