Modeling and forecasting of manufacturing variations

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2001-January, Issue , 2001, Pages 145-149

  Nassif, S R ^a  

^a IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

Circuit simulation; Design methodology; Geometry; Integrated circuit modeling; Power supplies; Predictive models; Solid modeling; Temperature; Virtual manufacturing; Wire

Indexed keywords

AGILE MANUFACTURING SYSTEMS; COMPUTER AIDED DESIGN; DESIGN; GEOMETRY; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUITS; MANUFACTURE; TEMPERATURE; WIRE;

DESIGN METHODOLOGY; INTEGRATED CIRCUIT MODELING; POWER SUPPLY; PREDICTIVE MODELS; SOLID MODEL; VIRTUAL MANUFACTURING;

CIRCUIT SIMULATION;

EID: 84949743191     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2001.913295     Document Type: Conference Paper

References (20)

1. S. W. Director and W. Maly, editors. Statistical Approach to VLSI, volume 8 of Advances in CAD for VLSI. North-Holland, 1994.
2. J. Power, B. Donnellan, A. Mathewson, and W. Lane. Relating statistical mosfet model parameter variabilities to ic manufacturing process fluctuations enabling realistic worst case design. IEEE Trans. Semiconductor Manufacturing, Aug 1994.
3. A. Misaka, A. Goda, K. Matsuoka, H. Umimoto, and S. Odanaka. A statistical critical dimension control at cmos cell level. In Proceedings of IEDM, 1996.
4. S. R. Nassif. Within-chip variability analysis. In Proceedings of IEDM, 1998.
5. M. Eisele, J. Berthold, D. Schmitt-Landseidel, and R. Mahnkopf. The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits. IEEE Trans. VLSI, Dec 1997.
6. The National Technology Roadmap for Semiconductors, 1997.
7. C. Alpert, A. Devghan, and S. Quay. Buffer insertion with accurate models for gate and interconnect delay. In Proceedings of DAC, 1999.
8. M. McKay, R. Beckman, and W. Conover. A comparison of three methods fos selecting values for input variables in the analysis of output from computer codes. Technometrics, May 1979.
9. L. W. Nagel. SPICE2: A Computer Program to Simulate Semiconductor Circuits. PhD thesis, University of California, Berkeley, 1975.
10. Y. Cheng, M. Chan, K. hui, M. Jeng, Z. Liu, J. Huang, K. Chen, J. Chen, R. Tu, P. Kp, and C. Hu. BSIM3v3 Manual. EECS Dept, Berkeley, 1996.
11. C. Michael and M. Ismail. Statistical Modeling for Computer-Aided Design of MOS VLSI Circuits. Kluwer, 1993.
12. A. Dharchoudhury et. al. Design and analysis of power distribution networks in powerpc™ microprocessors. In Proceedings of DAC, 1998.
13. M. K. Gowan, L. L. Biro, and D. B. Jackson. Power considerations in the design of the alpha 21264 microprocessor. In Proceedings of DAC, 1998.
14. G. Steele et. al. Full-chip verification methods for dsm power distribution systems. In Proceedings of DAC, 1998.
15. Y. M. Jiang and K. T. Cheng. Analysis of performance impact caused by power supply noise in deep submicron devices. In Proceedings of DAC, 1999.
16. S. Nassif and J. Kozhata. Fast power grid simulation. In Proceedings of DAC, 2000.
17. G. Digele, S. Lindenkreuz, and E. Kasper. Fully coupled dynamic electro-thermal simulation. IEEE Trans. VLSI, Sep 1997.
18. V. Szekely, A. Poppe, A. Pahi, A. Csendes, G. Hajas, and M. Rencz. Electro-thermal and logi-thermal simulation of vlsi designs. IEEE Trans. VLSI, Sep 1997.
19. B. E. Stine, D. S. Boning, and J. E. Chung. Analysis and decomposition of spatial variation in integrated circuit processes and devices. IEEE Trans. Semiconductor Manufacturing, Feb 1997.
20. C. Yu, T. Maung, C. Spanos, D. Boning, J. Chung, H. Liu, K. Chang, and D. Bertelink. Use of short-loop electrical measurements for yield improvement. IEEE Trans. Semiconductor Manufacturing, May 1995.