Load and store reuse using register file contents

Proceedings of the International Conference on Supercomputing

Volumn , Issue , 2001, Pages 289-302

  Onder S ^a   Gupta, R ^a  

^a Michigan Technological University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMPUTER HARDWARE; MULTITASKING; OPTIMIZATION;

VALUE ADDRESS ASSOCIATION STRUCTURES (VAAS);

STORAGE ALLOCATION (COMPUTER);

EID: 0034824934     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/377792.377850     Document Type: Conference Paper

References (22)

1. Load-reuse analysis: Design and evaluation
2. Memory dependence prediction using store sets
3. A new kind of memory for referencing arrays and pointers
4. The store-load address table and speculative register promotion
5. Using value prediction to increase the power of speculative execution hardware
6. A novel renaming scheme to exploit value temporal locality through physical register reuse and unification
7. Filter cache: An energy efficient memory structure
8. On the value locality of store instructions
9. Value locality and load value prediction
10. Pipeline gating: Speculation control for energy reduction
11. Delaying physical register allocation through virtual-physical registers
12. Streamlining inter-operation memory communication via data dependence prediction
13. Read-after-read memory dependence prediction
14. Dynamic speculation and synchronization of data dependences
15. Automatic generation of microarchitecture simulators
16. Dynamic memory disambiguation in the presence of out-of-order store issuing
17. Dynamic instruction reuse
18. Storageless value prediction using prior register values
19. Energy-efficient load and store reuse
20. Load redundancy removal through instruction reuse
21. Frequent value locality and value-centric data cache design