Transparent dynamic optimization: The design and implementation of dynamo

HP Laboratories Technical Report

Volumn , Issue 78, 1999, Pages

  Bala, Vasanth ^a   Duesterwald, Evelyn ^a   Banerjia, Sanjeev ^a  

^a HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

Binary translation; Compiler; Dynamic optimization; Trace selection

Indexed keywords

BINARY SEQUENCES; COMPUTER OPERATING SYSTEMS; COMPUTER PROGRAM LISTINGS; COMPUTER PROGRAMMING LANGUAGES; COMPUTER SIMULATION; LOGIC DESIGN; OPTIMIZATION; PROGRAM COMPILERS; USER INTERFACES;

DYNAMIC OPTIMIZATION; DYNAMO; HARDWARE SUPPORT; HPUX OPERATING SYSTEMS;

DYNAMIC PROGRAMMING;

EID: 5444263997     PISSN: None     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (65)

1. Ammons, G., Ball, T., and Larus, J.R. 1997. Exploiting hardware performance counters with flow and context sensitive profiling. ACM Sigplan Notices 32, June. 85-96.
2. th ACM Symposium of Operating Systems Principles. 1-14.
3. Auslander, J., Philipose, M., Chambers, C., Eggers, S.J., and Bershad, B.N. 1996. Fast, effective dynamic compilation. In Proceedings of the SIGPLAN'96 Conference on Programming Language Design and Implementation (PLDI'96).
4. Ayers, A., De Jong, S., Peyton, J., and Schooler, R. 1998. Scalable cross-module optimization. In Proceedings of the SIGPLAN'98 Conference on Programming Language Design and Implementation (PLDI'98), Montreal. 301-312.
5. Bala, V. and Freudenberger, S. 1996. Dynamic optimization: the DYNAMO project at HP Labs Cambridge (project proposal). Hewlett Packard Laboratories internal memo, Feb 1996.
6. Ball, T. and Larus, J.R. 1993. Branch prediction for free. In Proceedings of the SIGPLAN '93 Conference on Programming Language Design and Implementation. 300-313.
7. th Annual International Symposium on Microarchitecture (MICRO-29), Paris. 46-57.
8. Banerjia, S., Sathaye, S.W., Menezes, K.N., and Conte, T.M. 1998. MPS: miss-path scheduling for multiple-issue processors. IEEE Trans. Computers 47, 12 (Dec.).
9. Bedichek, R. 1995. Talisman: fast and accurate multicomputer simulation. In Proceeding 1995 ACM SIGMETRICS Conference on Measurement and Modeling of Computer Systems.
10. Bodik, R., Gupta, R., and Soffa, M.L. 1998. Complete removal of redundant expressions. In Proceedings of the SIGPLAN'98 Conference on Programming Language Design and Implementation (PLDI'98), Montreal. 1-14.
11. Buzbee, W.B. 1998. System and method of using annotations to optimize dynamically translated code in the presence of signals. U.S. Patent 5,838,978. Nov 1998.
12. Chernoff, A., Herdeg, M., Hookway, R., Reeve, C., Rubin, N., Tye, T., Yadavalli, B., and Yates, J. 1998. FX!32: a profile-directed binary translator. IEEE Micro, Vol 18, No. 2, March/April 1998.
13. Cmelik, R.F. and Keppel, D. 1993. Shade: a fast instruction set simulator for execution profiling. Technical Report UWCSE-93-06-06, Dept. Comp. Science and Engineering, Univ. Washington.
14. Cmelik, R.F. and Keppel, D. 1994. Shade: a fast instruction set simulator for execution profiling. ACM Sigmetrics Conference on the Measurement and Modeling of Computer Systems.
15. Cohn, R., Goodwin, D.W., and Lowney, P.G. 1997. Optimizing Alpha executables on Windows NT with Spike. Digital Technical Journal 9, 4.
16. th Annual Internation Symposium on Microarchitecture (MICRO-29), Paris. 80-89.
17. Consel, C. and Noel, F. 1996. A general approach for run-time specialization and its application to C. In Proceedings of the 23th Annual Symposium on Principles of Programming Languages. 145-156.
18. Conte, T.M., Patel, B.A., Menezes, K.N., and Cox, J.S. 1996. Hardware-based profiling: An effective technique for profile-driven optimization. International Journal of Parallel Programming 24, April. 187-206.
19. th Annual International Symposium on Microarchitecture (MICRO-28). 208-218.
20. Cooper, K., Hall M.H., and Kennedy, K. 1993. A methodology for procedure cloning. Computer Languages 19, 2 (April). 105-117.
21. Cramer, T., Friedman, R., Miller, T., Seberger, D., Wilson, R., and Wolczko, M. 1997. Compiling Java Just In Time. IEEE Micro, May/Jun 1997.
22. Duesterwald, E., Gupta, R., and Soffa, M.L. 1993. A practical data flow framework for array reference analysis and its use in optimization. In Proceedings of the SIGPLAN '93 Conference on Programming Languages Design and Implementation. 68-77.
23. nd Symposium on Principles of Programming Languages. 37-48.
24. th Annual International Symposium on Computer Architecture. 26-37.
25. Engler, D.R. 1996. VCODE: a retargetable, extensible, very fast dynamic code generation system. In Proceedings of the SIGPLAN'96 Conference on Programming Language Design and Implementation (PLDI'96).
26. th Annual International Symposium on Computer Architecture. 140-150.
27. st Annual Internation Symposium on Microarchitecture (MICRO-31), Dallas. 173-181.
28. Griswold, D. 1998. The Java HotSpot virtual machine architecture. Sun Microsystems, Mar. 1998. Available from http://java.sun.com/products/hotspot/ whitepaper.html.
29. Gwennap, L. 1997. Intel and HP make EPIC disclosure. Microprocessor Report 11, 14 (Oct.).
30. Gwennap, L. 1994. PA-7200 enables inexpensive MP systems. Microprocessor Report 8, 3 (Mar.).
31. Herold, S.A. 1998. Using complete machine simulation to understand computer system behavior. Ph.D. thesis, Dept. Computer Science, Stanford University.
32. Hewlett Packard 1996. HP-UX Release 10.20 Reference Manual. (Jul).
33. Hohensee, P., Myszewski, M., and Reese, D. 1996. Wabi cpu emulation. In Proceedings Hot Chips VIII.
34. Holzle, U. 1994. Adaptive optimization for SELF: reconciling high performance with exploratory programming, PhD thesis, Computer Science Dept., Stanford University, available as Technical Report STAN-CS-TR-94-1520. Also available as a Sun Microsystems Lab technical report.
35. Hookway, R.J, and Herdeg, M.A. 1997. Digital FX!32: combining emulation and binary translation. Digital Technical journal, Vol 9, No. 1, 1997, pp 3-12.
36. Hunt, Doug 1999. Private communication.
37. Hsu, W. 1999. Private communication.
38. Hwu, W.W., Mahlke, S.A., Chen, W.Y., Chang, P. P., Warter, N.J., Bringmann, R.A., Ouellette, R.Q., Hank, R.E., Kiyohara, T., Haab, G.E., Holm, J.G., and Lavery, D.M. 1993. The superblock: an effective structure for VLIW and superscalar compilation. The Journal of Supercomputing 7, (Jan.). 229-248.
39. Insignia 1991. SoftWindows for Macintosh and UNIX. http://www.insignia. com.
40. th Ann. Microprocessor Forum, San Jose, CA.
41. Kelly, E.K., Cmelik, R.F., and Wing, M.J. 1998. Memory controller for a microprocessor for detecting a failure of speculation on the physical nature of a component being addressed. U.S. Patent 5,832,205, Nov. 1998.
42. Knoop, J., Ruething, O., and Steffen, B. 1994. Optimal code motion: theory and practice. ACM Transactions on Programming Languages and Systems 16, 4. 1117-1155.
43. Knuth, D.E. 1973. The Art of Computer Programming: Volume 1 Fundamental Algorithms, Reading: MA: Addison-Wesley Publishing Co.
44. Kumar, A. 1996. The HP PA-8000 RISC CPU: a high performance out-of-order processor. In Proceedings Hot Chips VIII, Palo Alto, CA.
45. Leone, M. and Dybvig, R.K. 1997. Dynamo: a staged compiler architecture for dynamic program optimization. Technical Report #490, Dept. Computer Science, Indiana University.
46. Leone, M. and Lee, P. 1996. Optimizing ML with run-time code generation. In Proceedings of the SIGPLAN'96 Conference on Programming Language Design and Implementation. 137-148.
47. May, C. 1987. Mimic: a fast System/370 simulator. ACM SIGPLAN 1987 Symposium on Interpreters and Interpretive techniques.
48. Morel, E. and Renvoise, C. 1979. Global optimization by suppression of partial redundancies. CACM 22, 2. 96-103.
49. th Annual International Symposium on Computer Architecture, Denver. 13-25.
50. Pan, S., So, K., and Rahmeh, J. 1992. Improving the accuracy of dynamic branch prediction using branch correlation. In Proceedings of ASPLOS-V. 76-84.
51. Papworth, D. 1996. Tuning the Pentium Pro microarchitecture. IEEE Micro, (Apr.). 8-15.
52. Peleg, A. and Weiser, U. 1994. Dynamic flow instruction cache memory organized around trace segments independent of virtual address line. U.S. patent 5,381,533.
53. Poletta, M., Engler, D.R., and Kaashoek, M.F. 1997. tcc: a system for fast flexible, and high-level dynamic code generation. In Proceedings of the SIGPLAN '97 Conference on Programming Language Design and Implementation. 109-121.
54. th Annual International Symposium on Microarchitecture (MICRO-29), Paris. 24-35.
55. Sannella, M., Maloney, J., Freeman-Benson, B., and Borning, A. 1993. Multi-way versus one-way constraints in user interfaces: experiences with the DeltaBlue algorithm. Software - Practice and Experience 23, 5 (May). 529-566.
56. Sites, R.L., Chernoff, A., Kirk, M.B., Marks, M.P., and Robinson, S.G. Binary Translation. Digital Technical Journal, Vol 4, No. 4, Special Issue, 1992.
57. Song, S.P. Denman, M., and Chang, J. 1995. The PowerPC 604 microproccesor", IEEE Micro, (Oct.). 8-17.
58. SPEC, Information on SPEC programs are available from the SPEC Web site at http://www.spec.org.
59. Stears, P. 1994. Emulating the x86 and DOS/Windows in RISC environments. In Proceedings Microprocessor Forum, San Jose, CA.
60. Wall, D.W. 1986. Global register allocation at link-time. In Proceedings of the SIGPLAN'86 Symposium on Compiler Construction. 264-275.
61. Wall, D.W. 1992. Systems for late code modification. Research Report 92/3, Digital Equipment Corp. Western Research Laboratory, 250 University Ave, Polo Alto, CA 94301.
62. Witchel, E. and Rosenblum R. 1996. Embra: fast and flexible machine simulation. In Proceedings of the SIGMETRICS '96 Conference on Measurement and Modeling of Computer Systems. 68-78.
63. Yeager, K.C. 1996. MIPS R10000 superscalar microprocessor. In IEEE Micro, Apr. 1996.
64. Young, C. and Smith, M.D. 1994. Improving the accuracy of static branch prediction using branch correlation. In Proceedings of ASPLOS-VI. 232-241.
65. th ACM Symposium on Operating Systems Principles. 15-26.