Speculative memory cloaking and bypassing

International Journal of Parallel Programming

Volumn 27, Issue 6, 1999, Pages 427-456

  Moshovos, Andreas ^a   Sohi, Gurindar S ^b  

^a Northwestern University   (United States)

^b University of Wisconsin Madison   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SYSTEMS PROGRAMMING; DATA COMMUNICATION SYSTEMS; RESPONSE TIME (COMPUTER SYSTEMS); STORAGE ALLOCATION (COMPUTER);

SPECULATIVE MEMORY BYPASSING; SPECULATIVE MEMORY CLOAKING;

BUFFER STORAGE;

EID: 0033284694     PISSN: 08857458     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1018776132598     Document Type: Article

References (28)

1. J. Dennis, Data flow supercomputers, IEEE Computer (November 1980).
2. A. H. Veen, Dataflow machine architectures, ACM Computing Surveys, Vol. 18 (December 1986).
3. A. Moshovos and G. Sohi, Streamlining inter-operation communication via data dependence prediction, Proc. MICRO-30 (December 1997).
4. A. Moshovos, Memory dependence prediction, Ph.D. thesis, University of Wisconsin-Madison, Madison, Wisconsin 53706 (December 1998).
5. G. Z. Chrysos and J. S. Emer, Memory dependence prediction using store sets, Proc. ISCA-25 (June 1998).
6. S. Jourdan, R. Ronen, M. Bekerman, B. Shomar, and A. Yoaz, A novel renaming scheme to exploit value temporal locality through physical register reuse and unification, Proc. MI-CRO-31 (December 1998).
7. M. H. Lipasti, C. B. Wilkerson, and J. P. Shen, Value locality and load value prediction, Proc. ASPLOS-VII (October 1996).
8. M. H. Lipasti and J. P. Shen, Exceeding the dataflow limit via value prediction, Proc. MICRO-29 (December 1996).
9. G. S. Tyson and T. M. Austin, Improving the accuracy and performance of memory communication through renaming, Proc. MICRO-30 (December 1997).
10. G. Kane, MIPS R2000/R3000 RISC Architecture, Prentice-Hall (1987).
11. K. M. Wilson, K. Olukotun, and M. Rosenblum, Increasing cache port efficiency for dynamic superscalar processors, Proc. ISCA-23 (May 1996).
12. M. Reilly and J. Edmondson, Performance simulation of an alpha microprocessor, IEEE Computer, Vol. 31, No. 5 (May 1998).
13. S. E. Breach, Design and evaluation of a multiscalar processor, Ph.D. thesis, University of Wisconsin-Madison, Madison, Wisconsin (December 1998).
14. A. Moshovos, S. Breach, T. N. Vijaykumar, and G. Sohi, Dynamic speculation and synchronization of data dependences, Proc. ISCA-24 (June 1997).
15. S. McFarling, Combining branch predictors, Technical Report TN-36, Digital Equipment Corp., WRL (June 1993).
16. T. M. Austin, D. N. Pnevmatikatos, and G. S. Sohi, Fast address calculation, Proc. ISCA-22 (June 1995).
17. T. M. Austin and G. S. Sohi, Zero-cycle loads: Microarchitecture support for reducing load latency, Proc. MICRO-28 (November 1995).
18. J.-L. Baer and T.-F. Chen, An effective on-chip preloading scheme to reduce data access penalty, Proc. Supercomputing (1991).
19. R. J. Eickemeyer and S. Vassiliadis, A load-instruction unit for pipelined processors, IBM J. Res. Dev., Vol. 37, No. 4 (July 1993).
20. M. Golden and T. Mudge, Hardware support for hiding cache latency, CSE-TR-152-93, University of Michigan, Department of Electrical Engineering and Computer Science (February 1991).
21. Y. Sazeides, S. Vassiliadis, and J. E. Smith, The performance potential of data dependence speculation and collapsing, Proc. MICRO-29 (December 1996).
22. B. Cheng, D. A. Connors, and W. Hwu, Compiler-directed early load-address generation, Proc. MICRO-31 (December 1998).
23. G. D. McNiven and E. S. Davidson, Analysis of memory referencing behavior for design of local memories, Proc. ISCA-15 (May 1988).
24. A. S. Huang and J. P. Shen, A limit study of local memory requirements using value reuse profiles, Proc. MICRO-28 (December 1995).
25. M. H. Lipasti, Value locality and speculative execution, Ph.D. thesis, Carnegie Mellon University, Pittsburgh, Pennsylvania (April 1997).
26. G. Reinman, B. Calder, D. Tullsen, G. Tyson, and T. Austin, Profile guided load marking for memory renaming, Technical Report CS98-593, University of California, San Diego, California (July 1998).
27. S. Kaxiras and J. Goodman, Improving CC-NUMA performance using instruction-based prediction, Proc. HPCA-5 (February 1999).
28. G. Reinman and B. Calder, Predictive techniques for aggresive load speculation, Proc. MICRO-31 (December 1998).