Noise metrics in flip-flop designs

IEICE Transactions on Information and Systems

Volumn E88-D, Issue 7, 2005, Pages 1501-1505

  Elgamel, Mohammed A ^a,b   Faisal, Md Ibrahim ^a,c   Bayoumi, Magdy A ^a,d,e  

^a UNIVERSITY OF LOUISIANA AT LAFAYETTE   (United States)

^b University of Louisiana at Lafayette   (United States)

^c VLSI Research Group

^d Center for Advanced Computer Studies CACS   (United States)

^e University of Louisiana at Lafayette ^*

Author keywords

Deep aubmicron; Flip flop; Low power; Noise immunity

Indexed keywords

COMPUTER SIMULATION; ENERGY UTILIZATION; INTEGRATED CIRCUIT LAYOUT; SPURIOUS SIGNAL NOISE; TRANSISTORS; VLSI CIRCUITS;

DEEP AUBMICRON; FLIP-FLOP DESIGNS; LOW POWER; NOISE IMMUNITY;

FLIP FLOP CIRCUITS;

EID: 26044475921     PISSN: 09168532     EISSN: 17451361     Source Type: Journal    
DOI: 10.1093/ietisy/e88-d.7.1501     Document Type: Article

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