Noise tolerant low voltage XOR-XNOR for fast arithmetic

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 2003, Pages 285-288

  Elgamel, Mohamed ^a   Goel, Sumeer ^a   Bayoumi, Magdy ^a  

^a UNIVERSITY OF LOUISIANA AT LAFAYETTE   (United States)

Author keywords

Deep submicron; Multipliers; Nanometer technology; Noise tolerant; XOR XNOR circuits

Indexed keywords

ADDERS; COMPUTER SIMULATION; ELECTRIC POTENTIAL; ENERGY UTILIZATION; MULTIPLEXING; MULTIPLYING CIRCUITS; NANOTECHNOLOGY; SPURIOUS SIGNAL NOISE;

NOISE TOLERANCE;

GATES (TRANSISTOR);

EID: 0038714014     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/764867.764882     Document Type: Conference Paper

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