Power issues related to branch prediction

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn 2002-January, Issue , 2002, Pages 233-244

  Parikh, D ^a   Skadron, K ^a   Zhang, Yan ^a   Barcella, M ^a   Stan, M R ^a  

^a University of Virginia   (United States)

Author keywords

Accuracy; Banking; Computer science; Detectors; Embedded computing; Energy consumption; Energy dissipation; Power dissipation; Probes; Process design

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SCIENCE; DETECTORS; ENERGY DISSIPATION; ENERGY UTILIZATION; PROBES; PROCESS DESIGN; PROGRAM PROCESSORS; SUPERCOMPUTERS;

ACCURACY; ACCURATE PREDICTION; BANKING; BRANCH PREDICTION; BRANCH TARGET BUFFERS; EMBEDDED COMPUTING; ON-CHIP STRUCTURES; SUBSTANTIAL REDUCTION;

ELECTRIC LOSSES;

EID: 84949743030     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2002.995713     Document Type: Conference Paper

References (29)

1. D. H. Albonesi. Selective cache ways: On-demand cache resource allocation. In Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture, pages 248-59, Nov. 1999.
2. R. I. Bahar and Srilatha Manne. Power and energy reduction via pipeline balancing. In Proceedings of the 28th Annual International Symposium on Computer Architecture, June 2001.
3. D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A framework for architectural-level power analysis and optimizations. In Proceedings of the 27th Annual International Symposium on Computer Architecture, pages 83-94, June 2000.
4. D. C. Burger and T. M. Austin. The SimpleScalar tool set, version 2.0. Computer Architecture News, 25(3):13-25, June 1997.
5. B. Calder and D. Grunwald. Next cache line and set prediction. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, pages 287-96, June 1995.
6. P.-Y. Chang, E. Hao, and Y. N. Patt. Alternative implementations of hybrid branch predictors. In Proceedings of the 28th Annual International Symposium on Microarchitecture, pages 252-57, Dec. 1995.
7. Digital Semiconductor. DECchip 21064/21064A Alpha AXP Microprocessors: Hardware Reference Manual, June 1994.
8. Digital Semiconductor. Alpha 21164 Microprocessor: Hardware Reference Manual, Apr. 1995.
9. S. Ghiasi, J. Casmira, and D. Grunwald. Using IPC variation in workload with externally specified rates to reduce power consumption. In Proceedings of the Workshop on Complexity-Effective Design, June 2000.
10. K. Ghose and M. Kamble. Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation. In Proceedings of the 1999 International Symposium on Low Power Electronics and Design, pages 70-75, Aug. 1999.
11. R. Gonzalez and M. Horowitz. Energy dissipation in general purpose microprocessors. IEEE Journal of Solid-State Circuits, 31(9), Sep. 1996.
12. D. Grunwald, A. Klauser, S Manne, and A. Pleszkun. Confidence estimation for speculation control. In Proceedings of the 25th Annual International Symposium on Computer Architecture, pages 122-31, June 1998.
13. D. A. Jiménez, S. W. Keckler, and C. Lin. The impact of delay on the design of branch predictors. In Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, pages 67-77, Dec. 2000.
14. R. E. Kessler, E. J. McLellan, and D. A. Webb. The Alpha 21264 microprocessor architecture. In Proceedings of the 1998 International Conference on Computer Design, pages 90-95, Oct. 1998.
15. J. Kin, M. Gupta, and W. Mangione-Smith. The filter cache: An energy-efficient memory structure. In Proceedings of the 30th Annual International Symposium on Microarchitecture, pages 184-93, Dec. 1997.
16. S. Manne, A. Klauser, and D. Grunwald. Pipeline gating: speculation control for energy reduction. In Proceedings of the 25th Annual International Symposium on Computer Architecture, pages 132-41, June 1998.
17. S. McFarling. Combining branch predictors. Tech. Note TN- 36, DEC WRL, June 1993.
18. S.-T. Pan, K. So, and J. T. Rahmeh. Improving the accuracy of dynamic branch prediction using branch correlation. In Proceedings of the Fifth International Conference on Architectural Support for Programming Languages and Operating Systems, pages 76-84, Oct. 1992.
19. D. Parikh, K. Skadron, Y. Zhang, M. Barcella, and M. R. Stan. Power issues related to branch prediction. Technical Report CS-2001-25, University of Virginia Department of Computer Science, Nov. 2001.
20. K. Skadron, P. S. Ahuja, M. Martonosi, and D. W. Clark. Improving prediction for procedure returns with return-address-stack repair mechanisms. In Proceedings of the 31st Annual ACM/IEEE International Symposium on Microarchitecture, pages 259-71, Dec. 1998.
21. K. Skadron, D. W. Clark, and M. Martonosi. Speculative updates of local and global branch history: A quantitative analysis. Journal of Instruction-Level Parallelism, Jan. 2000. (http://www.jilp.org/vol2).
22. K. Skadron, M. Martonosi, and D. W. Clark. A taxonomy of branch mispredictions, and alloyed prediction as a robust solution to wrong-history mispredictions. In Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques, pages 199-206, Oct. 2000.
23. J. E. Smith. A study of branch prediction strategies. In Proceedings of the 8th Annual International Symposium on Computer Architecture, pages 135-48, May 1981.
24. P. Song. UltraSparc-3 aims at MP servers. Microprocessor Report, pages 29-34, Oct. 27 1997.
25. Standard Performance Evaluation Corporation. SPEC CPU2000 Benchmarks. http://www.specbench.org/osg/cpu2000.
26. W. Tang, R. Gupta, and A. Nicolau. Design of a predictive filter cache for energy savings in high performance processor architectures. In Proceedings of the 2001 International Conference on Computer Design, pages 68-73, Sept. 2001.
27. J. Turley. ColdFire doubles performance with v4. Microprocessor Report, Oct. 26 1998.
28. S. J. E. Wilton and N. P. Jouppi. Cacti: An enhanced cache access and cycle time model. IEEE Journal of Solid-State Circuits, 31(5):677-88, May. 1996.
29. T.-Y. Yeh and Y. N. Patt. Two-level adaptive training branch prediction. In Proceedings of the 24th Annual International Symposium on Microarchitecture, pages 51-61, November 1991.