The effect of LAC doping on deep submicrometer transistor capacitances and its influence on device RF performance

IEEE Transactions on Electron Devices

Volumn 51, Issue 9, 2004, Pages 1416-1423

  Narasimhulu, K ^a   Desai, Madhav P ^a   Narendra, Siva G ^b   Rao, V Ramgopal ^a  

^a IEEE   (India)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEEP SUBMICROMETER TRANSISTOR; DRAIN VOLTAGE NOISE SPECTRAL DENSITIES; LATERAL ASYMMETRIC CHANNEL; RF CMOS;

CAPACITANCE; COMPOSITION EFFECTS; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC FIELD EFFECTS; ELECTRIC POTENTIAL; ELECTRON MOBILITY; GATES (TRANSISTOR); SEMICONDUCTOR DOPING; TRANSCONDUCTANCE;

MOSFET DEVICES;

EID: 4444331816     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.833589     Document Type: Article

References (26)

1. J. N. Burghartz, " Silicon RF technology- the two generic approaches," in Proc. ESSDERC, Stuttgart, Germany, Sept. 1997, pp. 143-153.
2. E. Abou-Allam, T. Manku, M. Ting, and M. S. Obrecht, "Impact of technology scaling on CMOS RF devices and circuits," in Proc. IEEE Custom Integrated Circuits Conf., May 2000, pp. 21-24.
3. M. Saito, M. Ono, R. Fujimoto, H. Tanimoto, T. I. N. Yoshitomi, H. S. O. T. Momose, and H. Iwai, "0.15 μm RF CMOS technology compatible with logic CMOS for low-voltage operation," IEEE Trans. Electron Devices, vol. 45, pp. 737-742, Mar. 1998.
4. L. E. Larson, "Silicon technology tradeoffs for radio-frequency/mixed-signal systems-on-a-chip," IEEE Trans. Electron Devices, vol. 50, pp. 683-699, Mar. 2003.
5. B. Razavi, "CMOS technology characterization for analog and RF design," IEEE J. Solid-State Circuits, vol. 34, pp. 268-276, Mar. 1999.
6. V. Kilchytska, A. Neve, L. Vancaillie, D. Levacq, S. Adriaensen, H. van Meer, K. De Meyer, C. Raynaud, M. Dehan, J. P. Raskin, and D. Flandre, "Influence of device engineering on the analog and RF performances of SOI MOSFETs," IEEE Trans. Electron Devices, vol. 50, pp. 577-588, Mar. 2003.
7. J. Y. Yang, K. Benaissa, D. Crenshaw, B. Williams, S. Sridhar, J. Ai, J. Boselli, S. Zhou, S. P. Tsang, S. Ashburn, P. Madhani, T. Blythe, and H. Shichijo, "0.1 μm RFCMOS on high resistivity substrate for system on chip (SOC) application," in IEDM Tech. Dig., 2002, pp. 667-670.
8. D. Buss, "Device issues in the integration of analog/RF functions in deep sub-micron digital CMOS," in IEDM Tech. Dig., Dec. 1999, pp. 423-426.
9. C. Fiegna, "The effect of scaling on the performance of small signal MOS amplifiers," in Proc. ISCAS, May 2000, pp. 733-736.
10. K. Bult, "Analog design in deep-sub-micron CMOS," Proc. ESSCIRC, pp. 1-17, 2000.
11. A. Chatterjee, "Transistor design issues in integrating analog functions with high-performance digital CMOS," in Symp. VLSI Tech. Dig., 1999, pp. 7-8.
12. G. A. Sai-Halasz, M. R. Wordeman, D. P. Kern, S. Rishton, and E. Ganin, "High transconductance and velocity overshoot in NMOS devices at the 0.1 μm gate-length level" IEEE Electron Device Lett., vol. 9, pp. 464-466, Sept. 1988.
13. V. R. Rao, W. Hansch, and I. Eisele, "Simulation, fabrication and characterization of high-performance planar-doped-barrier sub-100-nm channel MOSFETs," in IEDM Tech. Dig., Dec. 1997, pp. 464-466.
14. S. Odanaka and A. Hiroki, "Potential design and transport property of 0.1-μm MOSFET with asymmetric channel profile," IEEE Trans. Electron Devices, vol. 44, pp. 595-600, Apr. 1997.
15. H.-S. Chen, J. Zhao, C. S. Teng, L. Moberly, and R. Lahri, "Submicrometer large-angle-tilt implanted drain technology for mixed-signal applications," in IEDM Tech. Dig., 1994, pp. 811-814.
16. J. P. John, V. Ilderem, C. Park, J. Teplik, K. Klein, and S. Cheng, "A low voltage graded-channel MOSFET (LV-GCMOS) for sub 1-V microcontroller application," in VLSI Symp. Tech. Dig., June 1996, pp. 178-179.
17. B. Cheng, A. Inani, V. R. Rao, and J. C. S. Woo, "Channel engineering for high-speed sub- 1.0 V power supply deep submicrometer CMOS," in VLSI Symp. Tech. Dig., 1999, pp. 69-70.
18. B. Cheng, V. R. Rao, and J. C. S. Woo, "Exploration of velocity overshoot in a high-performance deep sub-100-nm SOI MOSFET with asymmetric channel profile," IEEE Electron Device Lett., vol. 20, pp. 538-540, Oct. 1999.
19. H. V. Deshpande, B. Cheng, and J. C. S. Woo, "Channel engineering for analog device design in deep submicron CMOS technology for system on chip applications," IEEE Trans. Electron Devices, vol. 49, pp. 1558-1565, Sept. 2002.
20. ISE-TCAD Manuals, Release 8.0 ed., 2000.
21. International Technology Roadmap for Semiconductors, 2001 ed..
22. K. Narasimhulu, D. K. Sharma, and V. R. Rao, "Impact of lateral asymmetric channel doping on deep submicrometer mixed-signal device and circuit performance," IEEE Trans. Electron Devices, vol. 50, pp. 2481-2489, Dec. 2003.
23. Y. Tsividis, Operation and Modeling of MOS Transistor, 2nd ed. New York: McGraw-Hill, 1999.
24. W. Shockley, J. A. Copeland, and R. P. James, "The impedance field method of noise calculation in active semiconductor devices," in Quantum Theory of Atoms, Molecules and the Solid State, P.-O. Loewdin, Ed. New York: Academic, 1966, pp. 537-563.
25. J.-P. Nougier, "Fluctuations and noise of hot carriers in semiconductor materials and devices," IEEE Trans. Electron Devices, vol. 41, pp. 2034-2049, Dec. 1994.
26. F. Bonani, G. Ghione, M. R. Pinto, and R. K. Smith, "Generation-Recombination noise modeling in semiconductor devices through population or approximate equivalent current density fluctuations," Solid State Electron., vol. 43, pp. 285-295, 1999.