A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 8, 2005, Pages 1680-1686

  Okaniwa, Yusuke ^a   Tamura, Hirotaka ^b   Kibune, Masaya ^b   Yamazaki, Daisuke ^b   Cheung, Tsz Shing ^b   Ogawa, Junji ^b   Tzartzanis, Nestoras ^c   Walker, William W ^c   Kuroda, Tadahiro ^a  

^a KEIO UNIVERSITY   (Japan)

^b FUJITSU LABORATORIES LTD   (Japan)

^c FUJITSU LABORATORIES OF AMERICA   (United States)

Author keywords

CMOS integrated circuits; Comparators; High speed integrated circuits

Indexed keywords

BANDWIDTH; BIT ERROR RATE; CAPACITANCE; ELECTRIC CURRENTS; ELECTRIC INDUCTORS; ELECTRIC POTENTIAL; FREQUENCY MODULATION; POWER AMPLIFIERS; SEMICONDUCTOR MATERIALS; TOPOLOGY;

CMOS RECEIVERS; CMOS TECHNOLOGY; COMPARATORS; HIGH-SPEED INTEGRATED CIRCUITS;

CMOS INTEGRATED CIRCUITS;

EID: 23744451801     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.852014     Document Type: Article

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