A 40Gb/s clock and data recovery circuit in 0.18μm CMOS technology

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Lee, Jri ^a   Razavi, Behzad ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CORRELATION DETECTORS; DEMULTIPLEXING; ELECTRIC CONVERTERS; FLIP FLOP CIRCUITS; JITTER; PHASE LOCKED LOOPS; VARIABLE FREQUENCY OSCILLATORS;

CLOCK AND DATA RECOVERY CIRCUIT; QUARTER-RATE PHASE DETECTOR;

CMOS INTEGRATED CIRCUITS;

EID: 0037630868     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. J. Kim and B. Kim, "A Low Phase-Noise CMOS LC Oscillator with a Ring Structure," ISSCC Dig. of Tech. Papers, pp. 430-431, Feb. 2000.
2. J. E. Rogers and J. R. Long, "A 10Gb/s CDR/DEMUX with LC Delay Line VCO in 0.18μm CMOS," ISSCC Dig. of Tech. Papers, pp. 254-255, Feb. 2002.
3. J. D. H. Alexander, "Clock Recovery from Random Binary Data," Electronics Letters, vol. 11, pp. 541-542, Oct. 1975.