A fully-integrated 40Gb/s clock and data recovery/1:4 DEMUX IC in SiGe technology

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 84-85+435

  Reinhold, M ^a   Dorschky, C ^a   Pullela, R ^a   Rose, E ^a   Mayer, P ^a   Paschke, P ^a   Baeyens, Y ^a   Mattia, J P ^a   Kunz, F ^a  

^a NOKIA RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEMULTIPLEXING; DETECTOR CIRCUITS; FREQUENCY DIVIDING CIRCUITS; JITTER; PHASE LOCKED LOOPS; VARIABLE FREQUENCY OSCILLATORS;

CLOCK AND DATA RECOVERY (CDR) CIRCUITS;

TIMING CIRCUITS;

EID: 0035060743     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. max and 11 ps gate delay
2. A plastic packaged 10 Gb/s BiCMOS clock and data recovery 1:4-Demultiplexer with external VCO
3. T silicon bipolar technology
4. Design considerations for very-high-speed si-bipolar IC's operating up to 50 Gb/s