A 10 Gb/s CDR/DEMUX with LC delay line VCO in 0.18 μm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 254-255+465+247

  Rogers, Jonathan E ^a   Long, John R ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; COMPUTER SIMULATION; DEMULTIPLEXING; ELECTRIC IMPEDANCE; OPTOELECTRONIC DEVICES; PHASE LOCKED LOOPS; SENSITIVITY ANALYSIS; SIGNAL RECEIVERS; SPURIOUS SIGNAL NOISE; VARIABLE FREQUENCY OSCILLATORS;

OPTOELECTRONIC DATA RECEIVERS;

CMOS INTEGRATED CIRCUITS;

EID: 0036105878     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. A two-chip 1.5-GBD serial link interface
2. A fully integrated SIGE receiver IC for 10-Gb/s data rate
3. A 10 Gb/s CMOS clock and data recovery circuit with frequency detection
4. The modeling, characterization, and design of monolithic inductors for silicon RFICs
5. A plastic packaged 10 Gb/s BiCMOS clock and data recovering 1:4-demultiplexer with external VCO