A 9.9 G-10.8 Gb/s rate-adaptive clock and data-recovery with no external reference clock for WDM optical fiber transmission

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 252-253+464+247

  Noguchi, H ^a   Tateyama, T ^a   Okamoto, M ^a   Uchida, H ^a   Kimura, M ^a   Takahashi, K ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; DEMULTIPLEXING; ELECTRIC POTENTIAL; FLIP FLOP CIRCUITS; JITTER; VARIABLE FREQUENCY OSCILLATORS; WAVELENGTH DIVISION MULTIPLEXING;

CLOCK AND DATA RECOVERY (CDR) CIRCUITS;

FIBER OPTIC NETWORKS;

EID: 0036110781     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. SiGe BiCMOS 3.3 V clock and data recovery circuits for 10Gb/s serial transmission systems
2. A fully integrated SiGe receiver LSI for 10 Gb/s data rate
3. 2.5 GHz 4-phase clock generator with scalable and no feedback loop architecture
4. A 10 Gb/s CMOS clock and data recovery circuit with frequency detection