40Gb/s 2:1 multiplexer and 1:2 demultiplexer in 120nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Kehrer, Daniel ^a,b   Wohlmuth, Hans Dieter ^a   Knapp, Herbert ^a   Wurzer, Martin ^a   Scholtz, Arpad L ^b  

^a INFINEON TECHNOLOGIES AG   (Germany)

^b VIENNA UNIVERSITY OF TECHNOLOGY   (Austria)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; BUFFER CIRCUITS; CMOS INTEGRATED CIRCUITS; DEMULTIPLEXING; ELECTRIC IMPEDANCE; ELECTRIC INDUCTORS; INTEGRATED CIRCUIT TESTING; MULTIPLEXING; SIGNAL NOISE MEASUREMENT; SPURIOUS SIGNAL NOISE; TIMING DEVICES;

DATA DEMULTIPLEXER; DATA MULTIPLEXER; DIFFERENTIAL INDUCTANCE; SINUSOIDAL CLOCK SIGNAL; VOLTAGE SWING;

PIPELINE PROCESSING SYSTEMS;

EID: 0037630788     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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2. A. Tanabe, M. Umetani, I. Fujiwara, T. Ogura, K. Kataoka, M. Okihara, H. Sakuraba, T. Endoh and F. Masuoka, "0.18μm CMOS 10Gb/s Multiplexer/Demultiplexer ICs Using Current Mode Logic with Tolerance to Threshold Voltage Fluctuation," J. of Solid-State Circuits, vol. 36, n. 6, pp.988-996, June 2001.
3. J.E. Rogers and J.R. Long, "A 10 Gb/s CDR/DEMUX with LC Delay Line VCO in 0.18μm CMOS," in ISSCC Digest of Technical Papers, pp.254-255, 2002.
4. M. M. Green, A. Momtaz, K. Vakilian, X. Wang, K.C. Jen, D. Chung, J. Cao, M. Caresosa, A. Hairapetian, I. Fujimori and Y. Cai, "OC-192 Transmitter in Standard 0.18μm CMOS," in ISSCC Digest of Technical Papers, pp.248-249, 2002.
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6. T. Schiml et al "A 0.13μm CMOS Platform with Cu/ Low-k Interconnects for System on Chip Applications," in VLSI Technology Digest of Technical Papers, pp.101-102, 2001.