-
3
-
-
0038040150
-
Architecture and Synthesis for Multi-Cycle Communication
-
Apr.
-
J. Cong, Y. Fan, X. Yang and Z. Zhang, "Architecture and Synthesis for Multi-Cycle Communication," in Proceedings of 2003 International Symposium on Physical Design, pp. 190-196, Apr. 2003.
-
(2003)
Proceedings of 2003 International Symposium on Physical Design
, pp. 190-196
-
-
Cong, J.1
Fan, Y.2
Yang, X.3
Zhang, Z.4
-
5
-
-
0030651961
-
FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits
-
Jun.
-
J. Cong and C. Wu, "FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits," in Proceedings of the 34th Design Automation Conference, pp. 644-649, Jun. 1997.
-
(1997)
Proceedings of the 34th Design Automation Conference
, pp. 644-649
-
-
Cong, J.1
Wu, C.2
-
7
-
-
0024866680
-
An Efficient Method of Computing Static Single Assignment
-
Jan.
-
R. Cytron, J. Ferrante, B. K. Rosen, M. N. Wegman and F. K. Zadek, "An Efficient Method of Computing Static Single Assignment," in Proceedings of ACM Symposium on Principles of Programming Languages, Jan. 1989.
-
(1989)
Proceedings of ACM Symposium on Principles of Programming Languages
-
-
Cytron, R.1
Ferrante, J.2
Rosen, B.K.3
Wegman, M.N.4
Zadek, F.K.5
-
9
-
-
84949817096
-
High-level Synthesis under Multi-Cycle Interconnect Delay
-
Jan.
-
J. Jeon, D. Kim, D. Shin and K. Choi, "High-level Synthesis under Multi-Cycle Interconnect Delay," in Proceedings of Asia and South Pacific Design Automation Conference, pp. 662-667, Jan. 2001.
-
(2001)
Proceedings of Asia and South Pacific Design Automation Conference
, pp. 662-667
-
-
Jeon, J.1
Kim, D.2
Shin, D.3
Choi, K.4
-
10
-
-
0035208967
-
Behavior-to-Placed RTL Synthesis with Performance-Driven Placement
-
Nov.
-
D. Kim, J. Jung, S. Lee, J. Jeon and K. Choi, "Behavior-to-Placed RTL Synthesis with Performance-Driven Placement," in Proceedings of International Conference on Computer Aided Design, pp. 320-326, Nov. 2001.
-
(2001)
Proceedings of International Conference on Computer Aided Design
, pp. 320-326
-
-
Kim, D.1
Jung, J.2
Lee, S.3
Jeon, J.4
Choi, K.5
-
13
-
-
0347498863
-
Synthesis and Optimization of Digital Circuits
-
G. D. Micheli, "Synthesis and Optimization of Digital Circuits," McGraw-Hill, 1994.
-
(1994)
McGraw-Hill
-
-
Micheli, G.D.1
-
14
-
-
0008647363
-
Understanding Retiming Through Maximum Average-Delay Cycles
-
M. C. Papaefthymiou, "Understanding Retiming Through Maximum Average-Delay Cycles," Mathematical Systems Theory, vol. 27, pp. 65-84, 1994.
-
(1994)
Mathematical Systems Theory
, vol.27
, pp. 65-84
-
-
Papaefthymiou, M.C.1
-
15
-
-
0024682923
-
Force-Directed Scheduling for Behavioral Synthesis of ASICs
-
Jun.
-
P. Paulin and J. Knight, "Force-Directed Scheduling for Behavioral Synthesis of ASICs," in IEEE Trans. on CAD, vol. 8(6), pp. 661-679, Jun. 1989.
-
(1989)
IEEE Trans. on CAD
, vol.8
, Issue.6
, pp. 661-679
-
-
Paulin, P.1
Knight, J.2
-
19
-
-
0038336002
-
Optimum and Heuristic Transformation Techniques for Simultaneous Optimization of Latency and Throughput
-
Mar.
-
M. B. Srivastava and M. Potkonjak, "Optimum and Heuristic Transformation Techniques for Simultaneous Optimization of Latency and Throughput," in IEEE Trans. on VLSI Systems, vol. 3(1), pp. 2-19, Mar. 1995.
-
(1995)
IEEE Trans. on VLSI Systems
, vol.3
, Issue.1
, pp. 2-19
-
-
Srivastava, M.B.1
Potkonjak, M.2
-
22
-
-
0346237866
-
-
Altera Web Site, http://www.altera.com.
-
-
-
-
23
-
-
0346237865
-
-
FFT package, http://momonga.t.u-tokyo.ac.jp/̃ooura/fft.html.
-
FFT Package
-
-
-
24
-
-
0346237861
-
-
SUIF compiler, http://suif.stanford.edu.
-
SUIF Compiler
-
-
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