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Volumn , Issue , 2003, Pages 536-543

Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; C (PROGRAMMING LANGUAGE); COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER ARCHITECTURE; DISTRIBUTED PARAMETER CONTROL SYSTEMS; PROGRAM COMPILERS; UNIX;

EID: 0346777484     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (15)

References (24)
  • 5
    • 0030651961 scopus 로고    scopus 로고
    • FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits
    • Jun.
    • J. Cong and C. Wu, "FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits," in Proceedings of the 34th Design Automation Conference, pp. 644-649, Jun. 1997.
    • (1997) Proceedings of the 34th Design Automation Conference , pp. 644-649
    • Cong, J.1    Wu, C.2
  • 13
    • 0347498863 scopus 로고
    • Synthesis and Optimization of Digital Circuits
    • G. D. Micheli, "Synthesis and Optimization of Digital Circuits," McGraw-Hill, 1994.
    • (1994) McGraw-Hill
    • Micheli, G.D.1
  • 14
    • 0008647363 scopus 로고
    • Understanding Retiming Through Maximum Average-Delay Cycles
    • M. C. Papaefthymiou, "Understanding Retiming Through Maximum Average-Delay Cycles," Mathematical Systems Theory, vol. 27, pp. 65-84, 1994.
    • (1994) Mathematical Systems Theory , vol.27 , pp. 65-84
    • Papaefthymiou, M.C.1
  • 15
    • 0024682923 scopus 로고
    • Force-Directed Scheduling for Behavioral Synthesis of ASICs
    • Jun.
    • P. Paulin and J. Knight, "Force-Directed Scheduling for Behavioral Synthesis of ASICs," in IEEE Trans. on CAD, vol. 8(6), pp. 661-679, Jun. 1989.
    • (1989) IEEE Trans. on CAD , vol.8 , Issue.6 , pp. 661-679
    • Paulin, P.1    Knight, J.2
  • 16
    • 0031622879 scopus 로고    scopus 로고
    • Parallel Algorithms for Simultaneous Scheduling, Binding and Floorplanning in High-Level Synthesis
    • May
    • P. Prabhakaran and P. Banerjee, "Parallel Algorithms for Simultaneous Scheduling, Binding and Floorplanning in High-Level Synthesis," in Proceedings of International Symposium on Circuits and Systems, pp. 372-376, May 1998.
    • (1998) Proceedings of International Symposium on Circuits and Systems , pp. 372-376
    • Prabhakaran, P.1    Banerjee, P.2
  • 19
    • 0038336002 scopus 로고
    • Optimum and Heuristic Transformation Techniques for Simultaneous Optimization of Latency and Throughput
    • Mar.
    • M. B. Srivastava and M. Potkonjak, "Optimum and Heuristic Transformation Techniques for Simultaneous Optimization of Latency and Throughput," in IEEE Trans. on VLSI Systems, vol. 3(1), pp. 2-19, Mar. 1995.
    • (1995) IEEE Trans. on VLSI Systems , vol.3 , Issue.1 , pp. 2-19
    • Srivastava, M.B.1    Potkonjak, M.2
  • 22
    • 0346237866 scopus 로고    scopus 로고
    • Altera Web Site, http://www.altera.com.
  • 23
    • 0346237865 scopus 로고    scopus 로고
    • FFT package, http://momonga.t.u-tokyo.ac.jp/̃ooura/fft.html.
    • FFT Package
  • 24


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.