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Volumn , Issue , 1996, Pages 33-38
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Layout-driven RTL binding techniques for high-level synthesis
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Author keywords
[No Author keywords available]
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Indexed keywords
ALGORITHMS;
COMPUTER AIDED DESIGN;
COMPUTER SIMULATION;
ELECTRIC NETWORK TOPOLOGY;
LOGIC DESIGN;
PERFORMANCE;
SCHEDULING;
HIGH LEVEL SYNTHESIS;
REGISTER TRANSFER LEVEL BINDING;
ELECTRIC NETWORK SYNTHESIS;
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EID: 0030399298
PISSN: 10801820
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (4)
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References (14)
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