Parallel algorithms for simultaneous scheduling, binding and floorplanning in high-level synthesis

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 6, Issue , 1998, Pages 372-376

  Prabhakaran, Pradeep ^a   Banerjee, Prithviraj ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; PARALLEL ALGORITHMS;

HIGH-LEVEL SYNTHESIS; TIMING DRIVEN SYNTHESIS;

ELECTRIC NETWORK SYNTHESIS;

EID: 0031622879     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (20)