Threshold voltage instability characteristics of HfO2 dielectrics n-MOSFETs

Microelectronics Reliability

Volumn 45, Issue 7-8, 2005, Pages 1051-1060

  Rhee, Se Jong ^a   Lee, Jack C ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; CRYSTALLIZATION; DIELECTRIC DEVICES; ELECTRIC POTENTIAL; GATES (TRANSISTOR); HAFNIUM COMPOUNDS; HIGH TEMPERATURE EFFECTS; INTEGRATED CIRCUITS; PERMITTIVITY; SILICA; STRESS ANALYSIS; STRONTIUM COMPOUNDS; THRESHOLD VOLTAGE; TRANSCONDUCTANCE;

BIPOLAR STRESS; CHANNEL MOBILITY; EQUIVALENT OXIDE THICKNESS (EOT); STRESS FREQUENCIES;

MOSFET DEVICES;

EID: 20344365061     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2005.01.006     Document Type: Article

References (32)

1. Semiconductor Industry Association, The International Technology Roadmap for Semiconductor, 2003.
2. T.-S. Chen, D. Hadad, V. Valu, V. Jiang, S.-H. Kuah, and P.C. McIntyre Ir-electroded BST thin film capacitors for 1 giga-bit DRAM application IEEE Int Electron Dev Meet 1996 679 682
3. G.D. Wilk, R.M. Wallace, and J.M. Anthony High-gate dielectrics: current status and materials properties considerations J Appl Phys 89 2001 5243 5275
4. C.J. Howard, T.M. Sabine, and F. Dickson Structural and thermal parameters for rutile and anatase Acta Cryst B47 1991 462 468
5. K.J. Hubbardand, and D.G. Schlom Thermodynamic stability of binary oxides in contact with silicon J Mater Res 11 1996 2757
6. 2 high-k Dielectrics. Technical Digest IEDM, 2000. p. 35.
7. Lee BH, Choi R, Kang LG, Gopalan S, Nieh R, Onishi K, et al. Characteristics of TaN gate MOSFET with ultrathin hafnium oxide (8-12Å). Technical Digest IEDM 2000. p. 39.
8. 2 CMOSFETs using poly-SiGe gate. Technical Digest International Symposium VLSI, 2002. p. 86.
9. 2 and Zr silicate gate dielectrics. Technical Digest IEDM, 2000. p. 27.
10. 2 gate dielectric MOSFETs with TaN electrode and Nitridation surface preparation. Technical Digest International Symposium VLSI, 2001. p. 15.
11. y advanced gate dielectrics with poly Si gate electrode. Technical Digest IEDM, 2002. p. 857.
12. 2. IEEE Reliability Physics Symposium, 2003. p. 46-50.
13. 2 metal oxide semiconductor field effect transistor Appl Phys Lett 85 2004 1286 1288
14. 2 gate dielectrics by using a nitrided Si surface J Vac Sci B22 3 2004 916 919
15. Shiraishi K, Yamada K, Torii K, Akasaka Y, Nakajima K, Kohno M, et al. Physics in Fermi level pinning at the PolySi/Hf-based high-k oxide interface. Technical Digest International Symposium VLSI, 2004. p. 108-9.
16. Makabe M, Kubota T, Kitano T. Bias-temperature degradation of PMOSFETs; Mechanism and suppression. IEEE Reliability Physics Symposium, 2000. p. 205-9.
17. Haggag A, McMahon W, Hess K, Cheng K, Lee J, Lyding J, et al. High-performance chip reliability from short-time-tests. IEEE Reliability Physics Symposium, 2000. p. 205-9.
18. N. Shiono, and T. Yashiro Jpn J Appl Phys 18 1979 1087
19. 2 interface under long-term positive as well as negative bias-temperature aging J Electrochem Soc 130 1983 138
20. G. Haller, M. Knoll, D. Braeunig, R. Wulf, and W.R. Fahrner Bias-temperature stress on metal-oxide-semiconductor structures as compared to ionizing irradiation and tunnel injection J Appl Phys 56 1984 1844
21. K.O. Jeppson, and C.M. Svensson Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices J Appl Phys 48 1977 2004
22. A. Goetzberger, A.D. Lopez, and R.J. Strain J Electrochem Soc 120 1973 90
23. LaRosa G, Guarin F, Rauch S, Acovic A, Lukaitis J, Crabbe E, et al. NBTI channel hot carrier effects in PMOSFETs in advanced CMOS technologies. IEEE Reliability Physics Symposium, 1997. p. 282-6.
24. C.E. Blat, E.H. Nicollian, and E.H. Poindexter Mechanism of negative-bias-temperature instability J Appl Phys 69 1991 1712
25. Chen YF, Lee MT, Lin MH, Chou CH, Chang WC, Huang SC, et al. Negative Bias Temperature Instability (NBTI) in Deep Sub-micron p + gate pMOSFETs. IEEE Integrated Reliability Workshop, 2000.
26. B.E. Dealet J Electrochem Soc 114 3 1967 266
27. Chaparala P, Shibley J, Lim P. Threshold Voltage Drift in PMOSFETs due to NBTI and HCI, IEEE Integrated Reliability Workshop, 2000.
28. Fong Y, Chen IC, Holland S, Lee J, Hu C. Dynamic Stressing of Thin Oxides, Technical Digest IEDM, 1995. p. 863.
29. 2. IEEE Reliability Physics Symposium, 2003. p. 46.
30. E. Rosenbaum, Z. Liu, and C. Hu Silicon dioxide breakdown lifetime enhancement under bipolar bias conditions IEEE Trans Electron Dev 40 1993 2287
31. Ghidini G, Brazzelli D, Clementi C, Pellizzer F. Charge trapping mechanism under dynamic stress and its effect on failure time. IEEE Reliability Physics Symposium 1999. p. 88.
32. 2 MOSFET's, Technical Digest IEDM, 2001. p. 659.