Process and reliability of air-gap Cu interconnect using 90-nm node technology

IEEE Transactions on Electron Devices

Volumn 52, Issue 3, 2005, Pages 352-359

  Noguchi, Junji ^a   Sato, Kiyohiko ^a   Konishi, Nobuhiro ^a   Uno, Syouichi ^a   Oshima, Takayuki ^a   Ishikawa, Kensuke ^a   Ashihara, Hiroshi ^a   Saito, Tatsuyuki ^a   Kubo, Maki ^a   Tamaru, Tsuyoshi ^a   Yamada, Youhei ^a   Aoki, Hideo ^a   Fujiwara, Tsuyoshi ^a  

^a HITACHI LTD   (Japan)

Author keywords

Air gaps; Capacitance; Copper; IC interconnections; Reliability; Seals; Stress

Indexed keywords

CAPACITANCE; COPPER; DIELECTRIC PROPERTIES; DRY ETCHING; INTEGRATED CIRCUIT MANUFACTURE; LEAKAGE CURRENTS; PERMITTIVITY; RELIABILITY; SCANNING ELECTRON MICROSCOPY; TRANSMISSION ELECTRON MICROSCOPY; VLSI CIRCUITS;

AIR GAPS; IC INTERCONNECTIONS;

CMOS INTEGRATED CIRCUITS;

EID: 20144375453     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.843886     Document Type: Article

References (13)

1. J. Noguchi, N. Miura, M. Kubo, T. Tamaru, H. Yamaguchi, N. Hamada, K. Makabe, R. Tsuneda, and K. Takeda, "Cu-ion-migration phenomena and its influence on TDDB lifetime in Cu metallization," in Proc. IRPS, 2003, pp. 287-292.
2. E. T. Ogawa, J. Kim, G. S. Haase, H. C. Mogul, and J. W. McPherson, "Leakage, breakdown, and TDDB characteristics of porous low-k silica-based interconnect dielectrics," in Proc. IRPS, 2003, pp. 166-172.
3. B. P. Shieh, L. C. Bassman, D. K. Kim, K. C. Saraswat, M. D. Deal, and J. P. McVittie, "Integration and reliability issues for low capacitance air-gap interconnect studies," in Proc. IITC, 1998, pp. 125-127.
4. O. Demolliens, Y. Morand, M. Fayolle, M. Cochet, M. Assous, H. Feldis, D. Louis, J. C. Royen Y. Gobil, G. Passemard, P. Maury, F. Jourdan, M. Cordeau, T. Morel, L. Perroud, L. Ulmer, J. F. Lugand, and D. Renaud, "Copper-SiOC-AirGap integration in a double level metal interconnect," in Proc. IITC, 2000, pp. 276-277.
5. 2 air gap interconnect for sub 0.1 micron CMOS technologies," in Proc. IITC 2001, pp. 298-300.
6. L. G. Gosset, V. Arnal, P. Brun, M. Broekaart, C. Monget, N. Casanova, M. Rivoire, J. C. Oberlin, and J. Torres, "Integration of SiOC air gaps in copper interconnects," Microelectron. Eng., vol. 70, pp. 274-279, 2003.
7. M. B. Anand, M. Yamada, and H. Shibata, "NURA: a feasible gas-dielectric interconnect process," in VLSI Symp. Tech. Dig., 1996, pp. 82-83.
8. J. Noguchi, T. Fujiwara, K. Sato, T. Nakamura, M. Kubo, S. Uno, K. Ishikawa, T. Saito, N. Konishi, Y. Yamada, and T. Tamaru, "Simple self-aligned air-gap interconnect process with Cu/FSG structure," in Proc. IITC, 2003, pp. 68-70.
9. T. Saito, T. Imai, J. Noguchi, M. Kubo, Y. Ito, S. Omori, N. Ohashi, T. Tamaru, and H. Yamaguchi, "A novel copper interconnection technology using self aligned metal Capping method," in Proc. IITC, 2001, pp. 15-17.
10. H. Aoki, K. Torii, T. Oshima, J. Noguchi, U. Tanaka, H. Yamaguchi, T. Saito, N. Miura, T. Tamaru, N. Konishi, S. Uno, S. Morita, T. Fujii, and K. Hinode, "Robust 130 nm-node Cu dual damascene technology with low-κ barrier SiCN," in IEDM Tech. Dig., 2001, pp. 76-79.
11. J. Noguchi, T. Oshima, U. Tanaka, K. Sasajima, H. Aoki, K. Sato, K. Ishikawa, T. Saito, N. Konishi, S. Hotta, S. Uno, and K. Kikushima, "Integration and reliability issues of Cu/SiOC interconnect for ArF /90 nm node SoC manufacturing," in IEDM Tech. Dig., 2003, pp. 527-530.
12. K. Kinoshita, M. Tada, T. Usami, M. Hiroi, T. Tonegawa, K. Shiba, T. Onodera, M. Tagami, S. Saitoh, and Y. Hayashi, "Process design methodology for via-shape-controlled, copper dual-damascene interconnects in low-k organic film," in IEDM Tech. Dig., 2000, pp. 257-260.
13. J. Noguchi, T. Saito, N. Ohashi, H. Ashihara, H. Maruyama, M. Kubo, H. Yamaguchi, D. Ryuzaki, K. Takeda, and K. Hinode, "Impact of low-κ dielectrics and barrier metals on TDDB lifetime of Cu interconnects," in Proc. IRPS, 2001, pp. 355-359.