Robust 130nm-node Cu dual damascene technology with low-k barrier SiCN

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2001, Pages 76-79

  Aoki, H ^a   Torii, K ^a   Oshima, T ^a   Noguchi, J ^a   Tanaka, U ^a   Yamaguchi, H ^a   Saito, T ^a   Miura, N ^a   Tamaru, T ^a   Konishi, N ^a   Uno, S ^a   Morita, S ^a   Fujii, T ^a   Hinode, K ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE MEASUREMENT; COPPER; DIELECTRIC MATERIALS; ELECTRIC BREAKDOWN; LEAKAGE CURRENTS; PERMITTIVITY; PROBABILITY; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTOR DEVICE STRUCTURES; SILICON COMPOUNDS; THERMAL STRESS;

CUMULATIVE PROBABILITY; DUAL DAMASCENE INTERCONNECTION TECHNOLOGY;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0035716238     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)