Process design methodology for via-shape-controlled, copper duai-damaseene interconnects in low-k organie film

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2000, Pages 257-260

  Kinoshita, K ^a   Tada, M ^a   Usami, T ^a   Hiroi, M ^a   Tonegawa, T ^a   Shiba, K ^a   Onodera, T ^a   Tagami, M ^a   Saitoh, S ^a   Hayashi, Y ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COPPER; ELECTRIC RESISTANCE; FLUOROCARBONS; MASKS; PLASMA APPLICATIONS; ULSI CIRCUITS;

COPPER DUAL DAMASCENCE INTERCONNECTS;

DIELECTRIC FILMS;

EID: 17344388439     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)