Room-temperature demonstration of low-voltage and tunable static memory based on negative differential conductance in silicon single-electron transistors

Applied Physics Letters

Volumn 85, Issue 25, 2004, Pages 6233-6235

  Saitoh, Masumi ^a   Harata, Hidehiro ^a,b   Hiramoto, Toshiro ^a  

^a INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

^b CHUO UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

LOW-PRESSURE CHAMICAL VAPOR DEPOSITION (LP-CVD); NEGATIVE DIFFERENTIAL CONDUCTANCE (NDC); SINGLE-ELECTRON TRANSISTORS (SET); SINGLE-HOLE TRANSISTORS (SHT);

CHEMICAL VAPOR DEPOSITION; CMOS INTEGRATED CIRCUITS; ELECTRIC CONDUCTIVITY; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; ELECTRON BEAM LITHOGRAPHY; ELECTRONS; MICROPROCESSOR CHIPS; OXIDATION; RANDOM ACCESS STORAGE; VLSI CIRCUITS;

MOSFET DEVICES;

EID: 19944382468     PISSN: 00036951     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.1839643     Document Type: Article

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