Investigation of performance metrics for interconnect stack architectures

International Workshop on System Level Interconnect Prediction, SLIP

Volumn , Issue , 2004, Pages 23-29

  Gupta, Puneet ^a   Kahng, Andrew B ^a   Kim, Youngmin ^b   Sylvester, Dennis ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b The Department of Civil and Environmental Engineering   (United States)

Author keywords

Back end metrics; Bandwidth; Energy; Interconnect stacks; Throughput; Via blockage

Indexed keywords

BANDWIDTH; LITHOGRAPHY; MATHEMATICAL MODELS; MULTILAYERS; SPURIOUS SIGNAL NOISE; THROUGHPUT;

BACK-END METRICS; INTERCONNECT STACKS; INTERLEVEL DIELECTRICS (ILD); VIA BLOCKAGE;

INTEGRATED CIRCUIT LAYOUT;

EID: 19544370028     PISSN: None     EISSN: 15445631     Source Type: Conference Proceeding    
DOI: 10.1145/966747.966753     Document Type: Conference Paper

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