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Volumn 2003-January, Issue , 2003, Pages 318-323

Test time minimization for hybrid BIST of core-based systems

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BUILT-IN SELF TEST; ITERATIVE METHODS;

EID: 84954435426     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2003.1250830     Document Type: Conference Paper
Times cited : (20)

References (13)
  • 1
    • 0030291568 scopus 로고    scopus 로고
    • Testing ICs: Getting to the core of the problem
    • November
    • B. T Murray, J. P. Hayes, "Testing ICs: Getting to the core of the problem," IEEE Transactions on Computer, Vol. 29, pp. 32-39, November 1996.
    • (1996) IEEE Transactions on Computer , vol.29 , pp. 32-39
    • Murray, B.T.1    Hayes, J.P.2
  • 6
    • 0031163752 scopus 로고    scopus 로고
    • Scheduling Tests for VLSI Systems Under Power Constraints
    • June
    • R. Chou, K. Saluja, and V. Agrawal, Scheduling Tests for VLSI Systems Under Power Constraints, IEEE Transactions on VLSI Systems, Vol. 5, No. 2, pp. 175-185, June 1997.
    • (1997) IEEE Transactions on VLSI Systems , vol.5 , Issue.2 , pp. 175-185
    • Chou, R.1    Saluja, K.2    Agrawal, V.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.