A hybrid BIST architecture and its optimization for SoC testing

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2002-January, Issue , 2002, Pages 273-279

  Jervan, G ^a   Peng, Z ^a   Ubar, R ^b   Kruus, H ^b  

^a LINKÖPING UNIVERSITY   (Sweden)

^b TALLINN UNIVERSITY OF TECHNOLOGY   (Estonia)

Author keywords

Automatic testing; Built in self test; Computer architecture; Cost function; Hardware; Optimization methods; Performance evaluation; Software testing; System testing; System on a chip

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; AUTOMATIC TESTING; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COST EFFECTIVENESS; COST FUNCTIONS; COSTS; HARDWARE; MICROPROCESSOR CHIPS; PROGRAMMABLE LOGIC CONTROLLERS; SEMICONDUCTOR DEVICE MANUFACTURE; SOFTWARE TESTING; SYSTEM-ON-CHIP; TABU SEARCH;

COST EFFECTIVE; DETERMINISTIC TEST PATTERN; OPTIMIZATION METHOD; OPTIMIZATION PROCEDURES; PERFORMANCE EVALUATION; PSEUDO-RANDOM TESTS; SYSTEM ON A CHIP; SYSTEM TESTING;

BUILT-IN SELF TEST;

EID: 84948459349     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2002.996750     Document Type: Conference Paper

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