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Volumn , Issue , 2000, Pages 134-140

Analysis and minimization of test time in a combined BIST and external test approach

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION TIME; DESIGN TIME; OPTIMUM TEST SETS; TEST TIME; TESTING TIME;

EID: 84893689452     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2000.840029     Document Type: Conference Paper
Times cited : (41)

References (9)
  • 1
    • 0032314038 scopus 로고    scopus 로고
    • Scan chain design for test time reduction in core-based ics
    • October
    • J. Aerts and E. J. Marinissen. Scan Chain Design for Test Time Reduction in Core-Based ICs. In Proc. of International Test Conference, pages 448-457, October 1998.
    • (1998) Proc. of International Test Conference , pp. 448-457
    • Aerts, J.1    Marinissen, E.J.2
  • 2
    • 84893639045 scopus 로고
    • On the role of independent fault sets in the generation of minimal test sets
    • October
    • S. B. Akers. On the Role of Independent Fault Sets in the Generation of Minimal Test Sets. In Proc. of International Test Conference, pages 465-472, October 1987.
    • (1987) Proc. of International Test Conference , pp. 465-472
    • Akers, S.B.1
  • 3
    • 0029406001 scopus 로고
    • Test set compaction for combinational circuits
    • November
    • J. S. Chang and C. S. Lin. Test Set Compaction for Combinational Circuits. IEEE Trans. on Computer- Aided Design, pages 1370-1378, November 1995.
    • (1995) IEEE Trans. on Computer- Aided Design , pp. 1370-1378
    • Chang, J.S.1    Lin, C.S.2
  • 4
    • 0032320384 scopus 로고    scopus 로고
    • Test set compaction algorithms for combinational circuits
    • November
    • I. Hamzaoglu and J. H. Patel. Test Set Compaction Algorithms for Combinational Circuits. In Proc. of Int. Conf. on CAD, pages 283-289, November 1998.
    • (1998) Proc. of Int. Conf. on CAD , pp. 283-289
    • Hamzaoglu, I.1    Patel, J.H.2
  • 5
    • 0027150951 scopus 로고    scopus 로고
    • Cost eective generation of minimal test sets for stuck at faults in combinational logic circuits
    • June
    • S. Kajihara, I. Pomeranz, K. Kinoshita, and M. Reddy. Cost Eective Generation of Minimal Test Sets for Stuck at Faults in Combinational Logic Circuits. In Proc. of the Design Automation Conf., pages 102-106, June 1998.
    • (1998) Proc. of the Design Automation Conf. , pp. 102-106
    • Kajihara, S.1    Pomeranz, I.2    Kinoshita, K.3    Reddy, M.4
  • 7
    • 0032307115 scopus 로고    scopus 로고
    • A novel test methodology for core-based system lsis and a testing time minimization problem
    • October
    • M. Sugihara, H. Date, and H. Yasuura. A Novel Test Methodology for Core-Based System LSIs and a Testing Time Minimization Problem. In Proc. of International Test Conference, pages 465-472, October 1998.
    • (1998) Proc. of International Test Conference , pp. 465-472
    • Sugihara, M.1    Date, H.2    Yasuura, H.3
  • 8
    • 0032305822 scopus 로고    scopus 로고
    • A test method- ology for core-based system lsis
    • December
    • M. Sugihara, H. Date, and H. Yasuura. A test method- ology for core-based system lsis. IEICE Trans. Funda- mentals, E81-A(12):2640-2645, December 1998.
    • (1998) IEICE Trans. Funda- Mentals , vol.E81-A , Issue.12 , pp. 2640-2645
    • Sugihara, M.1    Date, H.2    Yasuura, H.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.