An on-chip spectrum analyzer for analog built-in testing

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 21, Issue 3, 2005, Pages 205-219

  Méndez Rivera, Marcia G ^a   Valdes Garcia, Alberto ^a   Silva Martinez, Jose ^a   Sánchez Sinencio, Edgar ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

Analog IC test; Built in testing; Frequency response; Switched capacitor circuits

Indexed keywords

BANDPASS FILTERS; CMOS INTEGRATED CIRCUITS; FREQUENCY RESPONSE; FREQUENCY SYNTHESIZERS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; MICROELECTRONICS; SPECTRUM ANALYZERS;

ANALOG CIRCUITS; ANALOG IC TEST; DEVICE-UNDER-TEST (DUT); SWITCHED-CAPACITOR CIRCUITS;

BUILT-IN SELF TEST;

EID: 17444429277     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1007/s10836-005-6351-y     Document Type: Article

References (25)

1. K. Arabi and B. Kaminska, "Oscillation Built-in Self Test (OBIST) for Functional and Structural Testing of Analog and Mixed-Signal Integrated Circuits," Proc. Int. Test Conference, 1997, pp. 786-795.
2. J.L. Ausin, J.F. Duque-Carrillo, G. Torelli and E. Sanchez-Sinencio, "Switched-Capacitor Circuits with Periodical Nonuniform Individual Sampling," IEEE Trans. on Circuits and Systems II, vol. 50, no. 8, 2003.
3. F. Balestro, V. Fraisse, G. Martel, D. Morche, P. Senn, G. Le Tourneur, and Y. Mahieux, "A 3-V 0.5-μm CMOS A/D Audio Processor for a Microphone Array," IEEE Journal of Solid-State Circuits, vol. 32, no. 7, pp. 1122-1126, 1997.
4. A. Baschirotto, F. Servi, and R. Castello, "A 200-Ms/s 10-mW Switched-Capacitor Filter un 0.5-μm CMOS Technology," IEEE Journal Solid-State Circuits, vol. 35, no. 8, pp. 1215-1219, 2000.
5. A. Bicakci, C.-S Kim, S.-S. Lee, and C. Conroy, "A 700 mW CMOS Line Driver for ADSL Central Office Applications," Proc. IEEE Int. Solid-State Circuits Conference, pp. 414-503, 2003.
6. A. Chatterjee, B.C. Kim, and N. Nagi, "DC Built-in Self-Test for Linear Analog Circuits," IEEE Design & Test of Computers, pp. 26-33, 1996.
7. B. Dufort and G.W. Roberts, "On-Chip Analog Signal Generation for Mixed-Signal Built-in Self-Test," IEEE Journal Solid-State Circuits, vol. 34, no. 3, pp. 318-330, 1999.
8. M.M. Hafed, N. Abaskharoun, G.W. Roberts, "A 4-GHz Effective Sample Rate Integrated Test Core for Analog and Mixed-Signal Circuits," IEEE Journal Solid-State Circuits, vol. 37, no. 4. pp. 499-514, 2002.
9. J. Huang and K. Cheng, "A Sigma-Delta Modulation Based BIST Scheme for Mixed-Signal Circuits," in Proc. IEEE Design Automation Conference, 2000, pp. 605-610.
10. G. Huertas, D. Vázquez, E.J. Peralías, A. Rueda, and J.L. Huertas, "Testing Mixed-Signal Cores: A Practical Oscillation-Based Test in an Analog Macrocell," IEEE Design and Test of Computers, vol. 33, no.7, pp. 73-82, 2002.
11. IEEE Std. 1149.4-1999, IEEE Standard for a Mixed-Signal Test Bus, IEEE, 1999.
12. D.A. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, 1997, pp. 504-507.
13. U. Kac, F. Novae, F. Azais, P. Nouet, and M. Renovell, "Extending IEEE Std. 1149.4 Analog Boundary Modules to Enhance Mixed-Signal Test," IEEE Design & Test of Computers, vol. 20, no. 2, pp. 32-39, 2003.
14. M. Mendez-Rivera, J. Silva-Martinez, and E. Sánchez-Sinencio, "On-Chip Spectrum Analyzer for Built-in Testing Analog ICs," Proc. of the IEEE Int. Symposium on Circuits and Systems, vol. 5. pp. 61-64, 2003.
15. L.S. Milor, "A Tutorial Introduction to Research on Analog and Mixed-Signal Circuit Testing," IEEE Trans. on Circuits and Systems II, vol. 45, no. 10, pp. 1389-1047, 1998.
16. U.-K. Moon, "CMOS High-Frequency Switched-Capacitor Filters for Telecommunication Applications," IEEE Journal Solid-State Circuits, vol. 35, no. 2, pp. 212-220, 2000.
17. S. Nagaraj, "A Parasitic-Insensitive Area-Efficient Approach to Realizing Very large Time Constants in Switched-Capacitor Circuits," IEEE Trans. on Circuits and Systems II, vol. 36, no. 9, pp. 1210-1216, 1989.
18. M. Negreiros, L. Carbo and A.A. Susin, "A Statistical Sampler for a New On-Line Analog Test Method," Journal of Electronic Testing, vol. 19, no. 5, pp. 585-595, 2003.
19. H.C. Patangia and B. Zenone, "A Programmable Switched-Capacitor Sinewave Generator," Proc. IEEE Midwest Symposium on Circuits and Systems, vol. 1, pp. 165-168, 1994.
20. R. Schaumann and M.E. Van Valkenburg, Design of Analog Filters, Oxford University Press, 2001, pp. 697-704.
21. J. Silva-Martinez and E. Sánchez-Sinencio, "Excess Phase-Jitter Cancellation Method for SC Relaxation Oscillators," IEEE Transactions on Circuits and Systems-II, vol. 34, no. 6, pp. 695-700, 1987.
22. M. Steyaert, J. Janssens, B. De Muer, M. Borremans, and N. Itoh, "A 2-V CMOS Cellular Transceiver Front-End," IEEE Journal Solid-State Circuits, vol. 35, no. 12, pp. 1895-1907, 2000.
23. A. Valdes-Garcia, J. Silva-Martinez, and E. Sánchez-Sinencio, "An On-Chip Transfer Function Characterization System for Analog Built-in Testing," in Proc. IEEE VLSI Test Symposium, 2004, pp. 261-266.
24. A.Y. Valero-Lopez, A. Valdes-Garcia, and E. Sánchez-Sinencio, "Frequency Synthesizer for On-Chip Testing and Automated Tuning," in Proc. IEEE Int. Symposium on Circuits and Systems, May 2004, pp. 565-568.
25. P.N. Variyam and A. Chatterjee, "Digital-Compatible BIST for Analog Circuits Using Transient Response Sampling," IEEE Design & Test of Computers, pp. 106-115, July-Sept. 2000.