DC built-in self-test for linear analog circuits

IEEE Design and Test of Computers

Volumn 13, Issue 2, 1996, Pages 26-33

  Chatterjee, Abhijit ^a,c,d,e,f,g   Kim, Bruce C ^a,c,g,h,i,j   Nagi, Naveena ^b,k,l,m,n  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b LogicVision ^*

^c GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^d INDIAN INSTITUTE OF TECHNOLOGY KANPUR   (India)

^e UNIVERSITY OF ILLINOIS AT CHICAGO   (United States)

^f UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^g IEEE

^h GEORGIA TECH RESEARCH INSTITUTE   (United States)

ⁱ UNIVERSITY OF CALIFORNIA   (United States)

^j UNIVERSITY OF ARIZONA   (United States)

^k LogicVision Inc   (United States)

^l INDIAN INSTITUTE OF TECHNOLOGY ROORKEE   (India)

^m UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

ⁿ UNIVERSITY OF TEXAS AT AUSTIN   (United States)

more..

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER TESTING; FAILURE ANALYSIS; MATHEMATICAL MODELS; MATRIX ALGEBRA; THEOREM PROVING; TRANSFER FUNCTIONS;

BUILT IN SELF TEST (BIST); CIRCUIT UNDER TEST (CUT); LINEAR ANALOG CIRCUITS;

ANALOG COMPUTERS;

EID: 0030164673     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.500198     Document Type: Article

References (11)

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