A 4-GHz effective sample rate integrated test core for analog and mixed-signal circuits

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 4, 2002, Pages 499-514

  Hafed, Mohamed M ^a,b   Abaskharoun, Nazmy ^b,c   Roberts, Gordon W ^a,b  

^a IEEE   (Canada)

^b MCGILL UNIVERSITY   (Canada)

^c ANALOG DEVICES INC   (United States)

Author keywords

Automatic test equipment; Built in testing; Circuit testing; Design for testability; Mixed analog digital integrated circuits

Indexed keywords

AUTOMATIC TEST EQUIPMENT; CURVE TRACING; DELAYED CLOCK SUBSAMPLING MECHANISM; HIGH BANDWIDTH FRONT AND SAMPLING NETWORK; HIGH FREQUENCY NARROW BAND SIGNALS; INTEGRATED TEST CORE; MIXED SIGNAL CIRCUITS; SPURIOUS FREE DYNAMIC RANGE; SYSTEMS ON CHIP; VOLTAGE CONTROLLED DELAY LINE;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; AUTOMATIC TESTING; BANDWIDTH; BUILT-IN SELF TEST; CMOS INTEGRATED CIRCUITS; DESIGN FOR TESTABILITY; DIGITAL INTEGRATED CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE; LINEAR INTEGRATED CIRCUITS; SIGNAL TO NOISE RATIO; VOLTAGE CONTROL;

INTEGRATED CIRCUIT TESTING;

EID: 0036539266     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.991388     Document Type: Article

References (26)

1. Design of mixed-signal systems-on-a-chip
2. Toward a standard for embedded core test: An example
3. Hybrid built-in self test (HBIST) for mixed analogue/digital integrated circuits
4. Built-in self-test for analog to digital converters
5. Structure and concepts for current-based analog scan
6. A BIST scheme for SNR, gain tracking and frequency response test of a sigma-delta ADC
7. 2 random walk CMOS DAC
8. A continuously calibrated 12-b, 10-MS/s, 3.3-V A/D converter
9. An integration of memory-based analog signal generation into current DFT architectures
10. Design and optimization of LC oscillators
11. On-chip analog signal generation for mixed-signal built-in self-test
12. A multipass A/D conversion technique for extracting on-chip analog signals
13. A robust deep submicron programmable DC voltage generator
14. Early capture for boundary scan timing measurements
15. Testing and characterizing jitter in 100 Base-Tx and 155.52 Mbits/s ATM devices with a 1 Gsample/s AWG in an ATE system
16. Applications of on-chip samplers for test and measurement of integrated circuits
17. On-chip sampling in CMOS integrated circuits
18. Analog-to-digital converter survey and analysis
19. Digitizer error extraction in the nonlinearity test
20. A 10-b 15-MHz CMOS recycling two-step A/D converter
21. Custom analog low power design: The problem of low voltage and mismatch
22. Design techniques for high-speed, high-resolution comparators
23. Low-jitter process-independent DLL and PLL based on self-biased techniques