Extending IEEE Std. 1149.4 analog boundary modules to enhance mixed-signal test

IEEE Design and Test of Computers

Volumn 20, Issue 2, 2003, Pages 32-39

  Kač, Uroš ^a   Novak, Franc ^a,b   Azaïs, Florence ^c   Nouet, Pascal ^c,d   Renovell, Michel ^c  

^a JO EF STEFAN INSTITUTE   (Slovenia)

^b UNIVERSITY OF MARIBOR   (Slovenia)

^c LIRMM   (France)

^d UNIV MONTPELLIER   (France)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL CIRCUITS; GATES (TRANSISTOR); LOGIC DEVICES; SENSORS; THRESHOLD VOLTAGE; VECTORS;

IN-CIRCUIT TEST (ICT);

PRINTED CIRCUIT TESTING;

EID: 0037341197     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2003.1188260     Document Type: Article

References (13)

1. R.G. Bennetts, IEEE 1149.1 Test Access Port and Boundary-Scan Std., DFT Technology Backgrounders, Feb. 2001, http://www.semiconductorfabtech.com/dft/tutorial/bscan.PDF.
2. IEEE Std. 1149.1-2001, IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE, 2001.
3. K.P. Parker, J.E. McDermit, and S. Oresjo, "Structure and Metrology for an Analog Testability Bus," Proc. Inf'l Test Conf. (ITC 93), IEEE Press, 1993, pp. 309-317.
4. IEEE Std. 1149.4-1999, IEEE Standard for a Mixed-Signal Test Bus, IEEE, 1999.
5. A. Cron, "IEEE 1149.4-Almost a Standard," Proc. Int'l Test Conf. (ITC 97), IEEE Press, 1997, pp. 174-182.
6. K.P.Parker, The Boundary-Scan Handbook: Analog and Digital, Kluwer, 1998.
7. "JTAG Analog Extension Test Chip: Target Specification for the IEEE P1149.4 Working Group," Preliminary Review 012, Keith Lofstrom Integrated Circuits, Beaverton, Ore., 1998; http://grouper.ieee.org/groups/1149/4/kl1p.html.
8. K.P. Parker et al., "Design, Fabrication, and Use of Mixed-Signal IC Testability Structures," Proc. Int'l Test Conf. (ITC 97), IEEE Press, 1997, pp. 489-498.
9. S. Sunter et al., "A General Purpose 1149.4 IC with HF Analog Test Capabilities," Proc. Int'l Test Conf. (ITC 01), IEEE Press, 2001, pp. 38-45.
10. National Semiconductor, "Mixed-Signal Test, and the IEEE 1149.4 Standard," http://www.national.com/appinfo/scan/.
11. K. Lofstrom, "Early Capture for Boundary Scan Timing Measurements," Proc. Int'l Test Conf. (ITC 96), IEEE Press, 1996, pp. 417-422.
12. S. Sunter and B. Nadeau-Dostie, "Complete, Contactless I/O Testing-Reaching the Boundary in Minimizing Digital IC Testing Cost," Proc. Int'l Test Conf. (ITC 02), IEEE Press, 2002, pp. 446-455.
13. U. Kač et al., "Alternative Test Methods Using IEEE 1149.4," Proc. Design, Automation, and Test in Europe (DATE 00), IEEE CS Press, 2000, pp. 463-467.