Fully self-aligned 6F2 cell technology for low cost 1Gb DRAM

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1996, Pages 22-23

  Aoki, Masami ^a   Ozaki, Tohru ^a   Yamada, Takashi ^a   Kawaguchiya, Hitomi ^a   Ishibashi, Yutaka ^a   Hamamoto, Takeshi ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; LITHOGRAPHY; PRODUCT DESIGN; RANDOM ACCESS STORAGE;

BIT LINE OVER CAPACITOR; BIT LINE PLUG FABRICATION; DUAL ISOLATION STRUCTURE; DYNAMIC RANDOM ACCESS STORAGE; OPEN BIT LINE CELL LAYOUT; SELF ALIGNED CYLINDRICAL STACKED CAPACITOR;

CAPACITORS;

EID: 0029702081     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)