Trend in DRAM structures and processes to giga-bit generations

NEC Research and Development

Volumn 40, Issue 3, 1999, Pages 267-271

  Kasai, Naoki ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; ELECTRIC INSULATORS; ELECTRODES; PERMITTIVITY;

CONTACT PLUGS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0033365169     PISSN: 0547051X     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (12)

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2. M. Koyanagi, et al., "Novel High Density, Stacked Capacitor MOS RAM," IEDM Tech. Dig., pp. 348-351, 1978.
3. H. Sunami, et al., "A Corrugated Capacitor Cell (CCC) for Megabit Dynamic MOS Memories," IEDM Tech. Dig., pp. 806-808, 1982.
4. K. N. Kim, et al., "Highly Manufactuable 1Gb SDRAM," Symp. VLSI Technol. Dig. Tech. Pap., pp. 9-10, 1997.
5. H. Masuda, et al., "A 5 V-Only 64K Dynamic RAM Based on High S/N Design," IEEE J. Solid-State Circuits, SC-15, pp. 846-854, 1980.
6. W. F. Richardson, et al., "A Trench Transistor Cross-Point DRAM Cell," IEDM Tech. Dig., pp. 714-717, 1985.
7. S. Kimura, et al., "A New Stacked Capacitor DRAM Cell Characterized by a Storage Capacitor on a Bit-Line Structure," IEDM Tech. Dig., pp. 596-599, 1988.
8. N. Lu, et al., "The SPT Cell - A New Substrate-Plate Trench Cell for DRAMs," IEDM Tech. Dig., pp. 771-774, 1985.
9. 2 4-Gigabit DRAM Cell," IEDM Tech. Dig., pp. 25-28, 1997.
10. H. Watanabe, et al., "A New Stacked Capacitor Structure Using Hemispherical-Grain (HSG) Poly-Silicon Electrodes," Ext. Abs. ICSSDM, pp. 873-876, 1990.
11. 5 High-Density VLSI Dynamic Memory," IEEE Trans. Electron Devices, ED-29, pp. 368-376, 1982.
12. 3 for 256M DRAM," IEDM Tech. Dig., pp. 823-826, 1991.