ParlS: A parameterizable interconnect switch for networks-on-chip

Proceedings - 17th Symposium on Integrated Cicuits and Systems Design, SBCCI2004

Volumn , Issue , 2004, Pages 204-209

  Zeferino, Cesar Albenes ^a   Santo, Frederico G M E ^a   Susin, Altamiro Amadeu ^b  

^a UNIVERSIDADE DO VALE DO ITAJAÍ   (Brazil)

^b FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

FPGA; Networks on Chip; Systems on Chip

Indexed keywords

BIT ERROR RATE; COMPUTER ARCHITECTURE; DATA COMMUNICATION EQUIPMENT; HEURISTIC METHODS; INTERCONNECTION NETWORKS; LOGIC CIRCUITS; LOGIC DESIGN; QUALITY OF SERVICE; RANDOM ACCESS STORAGE; ROUTERS;

NETWORKS-ON-CHIP (NOC); ON-CHIP NETWORK (OCN); ROUTER ARCHITECTURES; SYSTEMS-ON-CHIP (SOC);

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 14244263844     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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