Power-Delay Product Minimization in High-Performance 64-bit Carry-Select Adders

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 3, 2004, Pages 235-244

  Nève, Amaury ^a,b   Schettler, Helmut ^b   Ludwig, Thomas ^b   Flandre, Denis ^a  

^a UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

^b IBM   (Germany)

Author keywords

Adder; Digital CMOS; High performance; Low power; Power delay product; Silicon on insulator technology

Indexed keywords

ADDERS; BIPOLAR TRANSISTORS; CAPACITANCE; ELECTRIC POTENTIAL; GATES (TRANSISTOR); LOGIC CIRCUITS; MICROELECTRONICS; MULTIPLEXING EQUIPMENT; SILICON ON INSULATOR TECHNOLOGY;

DIGITAL CMOS; HIGH PERFORMANCE; LOW POWER; POWER-DELAY PRODUCTS;

CMOS INTEGRATED CIRCUITS;

EID: 11144358193     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.824305     Document Type: Conference Paper

References (26)

1. T. H. Ning, "CMOS in the new millennium," in Proc. IEEE Custom Integrated Circuit Conf. (CICC), 2000, pp. 49-56.
2. V. De and S. Borkar, "Low power and high performance design challenges in future technologies," in Proc. Great Lakes Symp. VLSI, 2000, pp. 1-6.
3. European Semiconductor Industry Association, Japan Electronics and Information Industries Association, Korea Semiconductor Industry Association, Taiwan Semiconductor Industry Association, and Semi-conductor Industry Association, International Technology Roadmap for Semiconductors, System Drivers, 2001.
4. C. Nagendra, R. M. Owens, and M. J. Irwin, "Power-delay characteristics of CMOS adders," IEEE Trans. VLSI Syst., vol. 2, pp. 377-381, Sept. 1994.
5. S. Naffzifer, "A subnanosecond 0.5 μm. 64b adder," in Proc. IEEE Int. Solid-State Circuits Conf., Slide Supplement, 1996.
6. J. Hennessy, D. Patterson, and D. Goldberg, Computer Architecture, A Quantitative Approach, 2nd ed. San Mateo, CA: Morgan Kaufman, 1996.
7. M. Allam, M. Anis, and M. Elmasry, "Effect of technology scaling on digital CMOS logic styles," in Proc. IEEE Custom Integrated Circuits Conf. (CICC), 2000, pp. 19-1-1-19-1-8.
8. R. Yung, S. Rusu, and K. Shoemaker, "Future trend of microprocessor design," in Proc. ESSCIRC 2002, pp. 43-46.
9. V. De and S. Borkar, "Low power and high performance design challenges in future technologies," in Proc. Great Lakes Symp. VLSI, 2000, pp. 1-6.
10. P.-F. Lu, C.-T. Chuang, J. Ji, L. F. Wagner, C.-M. Hsieh, J. B. Kuang, L. L.-C. Hsu, M. M. Pelella, S.-F. Sanford, and C. J. Anderson, "Floating-body effects in partially depleted SOI CMOS circuits," IEEE J. Solid-State Circuits, vol. 32, pp. 1241-1253, Aug. 1997.
11. N. Subba, A. Salman, S. Mitra, D. E. Ioannou, and C. Tretz, "Pseudo-NMOS revisited: Impact of SOI on low power, high speed circuit design," in Proc. IEEE Int. SOI Conf., Oct. 2000, pp. 26-27.
12. C. R. Tretz, R. K. Montoye, and W. Reohr, "Ratioed CMOS: A low power high speed design choice in SOI technologies," in Proc. IEEE Int. SOI Conf., Oct. 2000, pp. 28-29.
13. J. M. Masgonty, C. Arm, and C. Piguet, "Technology- and power-supply-independent cell library," in Proc. IEEE Custom Integrated Circuits Conf. (CICC), 1991, pp. 25.5/1-25.5/4.
14. K. Hwang, Computer Arithmetic: Principles, Architecture and Design. New York: Wiley, 1979.
15. S. Zaker and J. Zahnd, "OPTIMOS: a branch-level digital circuit optimizer," in Proc. EURO ASIC, 1993, pp. 563-572.
16. G. A. Katopis, W. D. Becker, T. R. Mazzawy, H. H. Smith, C. K. Vakirtzis, S. A. Kuppinger, B. Singh, P. C. Lin, J. Bartells Jr., G. V. Kihlmire, P. N. Venkatachalam, H. I. Stoller, and J. L. Frankel, "MCM technology and design for the S/390 G5 system," IBM J. Res. Develop., vol. 43, no. 5/6, pp. 621-650, Sept.-Nov. 1999.
17. G. G. Shahidi, "SOI technology for the GHz era," IBM J. Res. Develop., vol. 46, no. 2/3, pp. 121-131, Mar/May 2002.
18. I. Aller and K. E. Kroell, "Detailed analysis of the gate delay variability in partially depleted SOI CMOS circuits," in Proc. IEEE Int. SOI Conf., Oct. 1999, pp. 40-41.
19. A. Nève, D. Flandre, H. Schettler, T. Ludwig, and G. Hellner, "Design of a branch-based 64-bit carry-select adder in 0.18 μm partially-depleted SOI CMOS," in Proc. Int. Symp. Low Power Electronics and Design (ISLPED), Aug. 2002, pp. 108-111.
20. K. Yano, T. Yamanaka, T. Nishida, M. Saito, K. Shimohigashi, and A. Shimizu, "A 3.8 ns CMOS 16 × 16-b multiplier using complementary pass-transistor logic," IEEE J. Solid-State Circuits, vol. 25, pp. 388-395, Apr. 1990.
21. K. Martin, Digital Integrated Circuit Design. Oxford, U.K.: Oxford Univ. Press, 2000.
22. S. J. Lee, R. Woo, and H. J. Yoo, "480 ps 64-bit race logic adder," in Symp. VLSI Circuits Dig. Tech. Papers, 2001, pp. 27-28.
23. J. J. Kim, R. Joshi, C.-T. Chuang, and K. Roy, "SOI-optimized 64-bit high-speed CMOS adder design," in Symp. VLSI Circuits Dig. Tech. Papers, 2002, pp. 122-125.
24. X. Bai, C. Visweswariah, P. Strenski, and D. Hathaway, "Uncertainty-aware circuit optimization," in Proc. 39th Design Automation Conf., June 2002, pp. 58-63.
25. D. Sastiak, J. Tran, F. Mounes-Toussi, and S. Storino, "A 2nd generation 440 ps SOI 64 b adder," in IEEE Int. Solid-State Circuits Conf., Feb. 2000, pp. 288-289.
26. M. Garg and A. Katoch, "Evaluation of skew tolerance in delayed clocking scheme for dynamic circuits," in Proc. ESSCIRC, Sept. 2001, pp. 396-399.