A 2nd generation 440ps SOI 64b adder

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 288-289

  Stasiak, D ^a   Tran, J ^a   Mounes Toussi, F ^a   Storino, S ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; CAPACITANCE; CMOS INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; SILICON ON INSULATOR TECHNOLOGY; SPURIOUS SIGNAL NOISE; THRESHOLD VOLTAGE;

FLOATING BODY EFFECTS;

ADDERS;

EID: 0034428381     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. A 0.2μm 1.8V SOI 550MHz 64b powerPCTM microprocessor with copper interconnects
2. A 0.18μm 1.5μ SOI 660MHz 64b powerPCTM microprocessor with copper interconnects
3. Partially-depleted SOI technology for digital logic