Design of a branch-based 64-bit carry-select adder in 0.18 μm partially depleted SOI CMOS

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 108-111

  Nève, Amaury ^a   Flandre, Denis ^a   Schettler, Helmut ^b   Ludwig, Thomas ^b   Hellner, Gerhard ^b  

^a UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

^b IBM   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; COPPER; METALLIZING; SILICON ON INSULATOR TECHNOLOGY;

CARRY-SELECT ADDER; PARTIALLY DEPLETED SILICON ON INSULATOR CMOS;

LOGIC DESIGN;

EID: 0036954655     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/566434.566438     Document Type: Conference Paper

References (7)

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2. Tretz C.R., Montoye R.K. and Reohr W., "Ratioed CMOS: a Low Power High Speed Design Choice in SOI Technologies", 2000 IEEE Int. SOI Conf., Oct. 2000, pp. 28-29.
3. Masgonty J.M., Arm C. and Piguet C., "Technology- and Power Supply-Independent Cell Library", IEEE Custom Integrated Circuits Conference, 1991, pp. 25.5.1-25.5.4.
4. Das K. and Brown R., "Evaluation of Circuit Approaches in Partially Depleted SOI-CMOS", 2000 IEEE Int. SOI Conference, pp. 98-99.
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6. Nève A. and Flandre D., "Branch-Based Logic for High Performance Carry-Select Adders in 0.25 um Bulk and Silicon-On-Insulator CMOS Technologies", PATMOS 2001, pp. 8.2.1-8.2.10.
7. Leobandung E., Barth E., Sherony M., Lo S.-H., Schulz R., Chu W., Khare M., Sadana D., Schepis D., Boiam R., Sleight I., White F., Assaderaghi F., Moy D., Biery G., Goldblan, R., Chen T.-C., Davari B. and Shahidi G., "High Performance 0.18 μm SOI CMOS Technology", International Electron Devices Meeting 1999, pp. 679-682.