Future trend of microprocessor design

European Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 43-46

  Yung, Robert ^a   Rusu, Stefan ^a   Shoemaker, Ken ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84893722381     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. G. Moore, "Cramming more components onto integrated circuits", Electronics, Vol. 38, No. 8, April 19, 1965.
2. R. Chau et.Al., "A 50nm Depleted-Substrate CMOS transistor (DST)", IEDM Tech. Digest, 2001.
3. S. Towle et.Al., "Bumpless Build-Up Layer Packaging", ASME Intl. Mech. Eng. Digest, 2001.
4. International Technology Roadmap for Semiconductors, 2001 edition.
5. Intel Microprocessor Reference Guide, April 2002. (http://www.intel.com/ pressroom/kits/quickref.htm)
6. Standard Performance Evaluation Corporation, April 2002. (http://www.spec.org)