MCM technology and design for the S/390 G5 system

IBM Journal of Research and Development

Volumn 43, Issue 5, 1999, Pages 621-650

  Katopis, George A ^a   Becker, W Dale ^a   Mazzawy, Toufie R ^a   Smith, Howard H ^a   Vakirtzis, C K ^b   Kuppinger, S A ^b   Singh, B ^b   Lin, P C ^b   Bartells Jr , J ^b   Kihlmire, G V ^b   Venkatachalam, P N ^b   Stoller, H I ^b   Frankel, J L ^b  

^a IBM   (United States)

^b NONE

Author keywords

[No Author keywords available]

Indexed keywords

CERAMIC MATERIALS; CLIENT SERVER COMPUTER SYSTEMS; CMOS INTEGRATED CIRCUITS; COOLING SYSTEMS; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT LAYOUT; MULTILAYERS;

CENTRAL ELECTRONIC COMPLEX; CHIP TECHNOLOGY;

MULTICHIP MODULES;

EID: 0033332974     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.435.0621     Document Type: Article

References (23)

1. E. A. Reese, D. Nedwek, J. Jex. M. Khaira, T. Burton, P. Nag, H. Kumar, C. Dike, D. Finan, and M. Haycock, "A Phase-Tolerant 3.8 GB/s Data Communication Router for a Supercomputer Backplane," ISSCC Digest of Technical Papers, February 1994, pp. 296-297.
2. G. A. Katopis and W. D. Becker, "S/390 Cost Performance Considerations for MCM Packaging Choices," IEEE Trans. Components, Packaging, & Manuf. Technol. B: Adv. Packaging 21, No. 3, 286-297 (August 1998).
3. W. D. Becker, H. Smith, T. McNamara, P. Muench, J. Eckhardt, M. McAllister, G. Katopis, S. Richter, R. Frech, and E. Klink, "Modeling, Simulation, and Measurement of Mid-Frequency Noise in Computer Systems," IEEE Trans. Components, Packaging, & Manuf. Technol. B: Adv. Packaging 21, No. 2. 157-163 (May 1998).
4. G. A. Katopis, W. D. Becker, H. H. Smith, and H. Stoller, "MCM C/D Design for the CMOS Implementation of the S/390 System," Proceedings of the 47th Electronic Components and Technology Conference, IEEE Cat. No. 97CH36048, May 1997, pp. 479-485.
5. E. E. Davidson, P. W. Harding, G. A. Katopis, M. O. Nealon, and L. L. Wu, "Physical and Electrical Design Features of the IBM Enterprise System/9000 Circuit Module," IBM J. Res. Develop. 36, No. 5, 277-288 (September 1992).
6. E. D. Perfecto, A. P. Giri, R. R. Shields. H. P. Longworth, J. R. Pennacchia, and M. P. Jeanneret, "Thin-Film Multichip Module Packages for High-End IBM Servers," IBM J. Res. Develop. 42, No. 5, 597-606 (September 1998).
7. H. Stoller, S. Ray, E. Perfecto, and T. Wassick, "Evolution of Engineering Change (EC) and Repair Technology in High Performance Multi-Chip Modules at IBM," Proceedings of the 48th Electronic Components and Technolog Conference, Seattle, WA, May 1998, pp. 916-921.
8. R. R. Livolsi, "Variable Voltage Driver," U.S. patent pending, Docket No. PO998062.
9. J. P. Eckhardt and K. A. Jenkins, "PLL Phase Error and Power Supply Noise," Proceedings of the 7th Topical Meeting on Electrical Performance of Electronic Packaging, West Point, NY, October 1998, pp. 73-76.
10. R. M. Averill III, K. G. Barkley, M. A. Bowen, P. J. Camporese, A. H. Dansky, R. F. Hatch, D. E. Huffman, M. D. Mayo, S. A. McCabe, T. G. McNamara, T. J. McPherson, G. A. Northrop, L. Sigal, H. Smith, D. A. Webber, and P. M. Williams, "Chip Integration Methodology for the IBM S/390 G5 and G6 Custom Microprocessors," IBM J. Res. Develop. 43, 681-706 (1999, this issue).
11. B. Singh, W. Becker, and M. McAllister, "Core Logic Simultaneous Switching Noise Measurements on a 500 MHz CMOS Chip on a CBGA SCM," Proceedings of the 48th Electronic Components and Technology Conference, Seattle, WA, May 1998, pp. 605-609.
12. B. D. McCredie and W. D. Becker, "Modeling, Measurement, and Simulation of Simultaneous Switching Noise," IEEE Trans. Components, Packaging, & Manuf. Technol. B: Adv. Packaging 19, No. 3, 461-472 (August 1996).
13. David P. Lapotin, Toufie R. Mazzawy, and Marlin L. White, "Early Package Analysis: Considerations and Case Study," IEEE Computer 26, No. 4, 30-39 (April 1993).
14. Rao R. Tummala, Eugene J. Rymaszewski, and Alan G. Klopfestein, Microelectronics Packaging Handbook, Second Edition, Part I, Chapter 3, Chapman & Hall, New York, 1997.
15. P. N. Venkatachalam, H. H. Smith, and R. Rippens, "Noise Containment in a High Wire Density Multichip Module," Proceedings of the 2nd Topical Meeting on Electrical Performance of Electronic Packages, October 20-22, 1993, pp. 58-60).
16. D. Rude, "Statistical Method of Noise Containment in a Synchronous System," IEEE Trans. Components, Packaging, & Manuf. Technol. 17, 514-519 (November 1994).
17. A. Feller, H. R. Kaupp, and J. J. DiGiacomo, "Cross-Talk and Reflections in High-Speed Digital Systems," AFIPS Conf. Proc. Fall Joint Computer Conference 27, 511-525 (1965).
18. B. J. Rubin, "An Electromagnetic Approach for Modeling High Performance Computer Packages," IBM J. Res. Develop. 34, No. 4, 585-600 (July 1990).
19. W. T. Weeks, "Calculations of Coefficients of Capacitance of Multi-Conductor Transmission Lines in the Presence of a Dielectric Interface," IEEE Trans. Microwave Theory MTT-18, 35-43 (1970).
20. J. F. Janak, D. D. Ling, and H. M. Huang, "C3DSTAR: A 3D Wiring Capacitance Calculator," Proceedings of the IEEE International Conference on Computer-Aided Design, November 1990, pp. 530-533.
21. G. Katopis, P. Lin, and P. N. Venkatachalam, "Coupled Noise Estimation for MCM Via Structures," Proceedings of NEPCON West 1992, February 1992, pp. 64-76.
22. H. H. Smith and C. T. Spring, "Coupled Noise Analysis of a Complex Connector Structure Using a Full-Wave Modeling Approach," Proceedings of NEPCON West 1992, February 1992, pp. 29-35.
23. H. H. Smith and G. A. Katopis, "Multireflection Algorithm for Timed Statistical Coupled Noise Checking," IEEE Trans. Components, Packaging, & Manuf. Technol. 19, 503-511 (August 1996).