Ratioed CMOS: A low power high speed design choice in SOI technologies

IEEE International SOI Conference

Volumn , Issue , 2000, Pages 28-29

  Tretz, Christophe R ^a   Montoye, Robert K ^a   Reohr, William ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; LOGIC GATES; MULTIPLEXING EQUIPMENT; SEMICONDUCTOR JUNCTIONS; SILICON ON INSULATOR TECHNOLOGY;

FLOATING-BODY EFFECTS; MULTIPLIER SHIFTERS;

CMOS INTEGRATED CIRCUITS;

EID: 0034471011     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)