SOI-optimized 64-bit high-speed CMOS adder design

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2002, Pages 122-125

  Kim, Jae Joon ^a   Joshi, Rajiv ^b   Chuang, Ching Te ^b   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; OPTIMIZATION; PERFORMANCE; SILICON ON INSULATOR TECHNOLOGY; SPURIOUS SIGNAL NOISE;

CARRY LOOKAHEAD ADDER; CARRY SELECT ADDER; FLOATING BODY EFFECT; PARTIALLY DEPLETED SILICON ON INSULATOR TECHNOLOGY; SENSE AMPLIFIER; SOFTWARE PACKAGE SPICE;

ADDERS;

EID: 0242611653     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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7. UFSOI 6.0 with UFPDB - 1.0, http://www.soi.tec.ufl.edu/ufsoi.html
8. J. Fossum, "Unified Process-Based Compact Model for PD/SOI and Bulk-Si MOSFETs, with Scaled CMOS Applications," SRC Annual Review, Jun. 2001.
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10. R. Puri and C. T. Chuang, "Hysteresis Effect in Pass-Transistor-Based, Partially Depleted SOI CMOS Circuits," IEEE Journal of Solid State Circuits, vol. 35, no. 4, pp.625-631, Apr. 2000